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1. 发明申请

US20060206842A1 Method for retiming in the presence of verification constraints 失效
标题翻译：在存在验证约束的情况下重新定时的方法
公开(公告)号：US20060206842A1
公开(公告)日：2006-09-14
申请号：US11077331
申请日：2005-03-10
申请人： Jason Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
发明人： Jason Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method, system and computer program product for performing retiming in the presence of constraints are disclosed. The method comprises receiving an initial design containing one or more targets and one or more constraints and enumerating the one or more constraints and the one or more targets into a retiming gate set. A retiming graph is constructed from the initial design, and a retiming solution is obtained on the retiming graph. The retiming solution is normalized. One or more retiming lags from the retiming graph are propagated to the initial design, and the initial design is verified by using a constraint-satisfying analysis to determine whether the one or more targets may be hit while the one or more constraints are satisfied.
摘要翻译：公开了一种用于在存在约束的情况下执行重新定时的方法，系统和计算机程序产品。该方法包括接收包含一个或多个目标和一个或多个约束的初始设计，并将一个或多个约束和一个或多个目标列举到重定时门组中。从初始设计构建重新定时图，并在重新定时图上获得重新定时解决方案。重新定时解决方案被归一化。来自重新定时图的一个或多个重新定时延迟被传播到初始设计，并且通过使用约束满足分析来确认初始设计，以确定在满足一个或多个约束的情况下是否可以命中一个或多个目标。

2. 发明申请

US20080066031A1 Method For Verification Using Reachability Overapproximation 失效
标题翻译：使用可达性过近似的验证方法
公开(公告)号：US20080066031A1
公开(公告)日：2008-03-13
申请号：US11938656
申请日：2007-11-12
申请人： Jason Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
发明人： Jason Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is expanded to create a superset of the first initial state containing one or more states reachable from the first initial state of the design. A superset is synthesized to define a second initial state of the design. Application of the superset to the design is overapproximated through cutpoint insertion into the superset to obtain a modified superset, and the property is verified with reference to the modified superset.
摘要翻译：公开了一种用于验证设计符合期望属性的方法，系统和计算机程序产品。该方法包括接收设计，设计的第一初始状态和关于设计的验证的属性。设计的第一初始状态被扩展以创建包含从设计的第一初始状态可访问的一个或多个状态的第一初始状态的超集。合成超集以定义设计的第二初始状态。超设计对设计的应用通过将切入点插入到超集中来获得修改后的超集，并且参考修改后的超集来验证该属性。

3. 发明申请

US20080052650A1 Method for Verification Using Reachability Overapproximation 失效
标题翻译：使用可达性过近似验证的方法
公开(公告)号：US20080052650A1
公开(公告)日：2008-02-28
申请号：US11938612
申请日：2007-11-12
申请人： Jason Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
发明人： Jason Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is expanded to create a superset of the first initial state containing one or more states reachable from the first initial state of the design. A superset is synthesized to define a second initial state of the design. Application of the superset to the design is overapproximated through cutpoint insertion into the superset to obtain a modified superset, and the property is verified with reference to the modified superset.
摘要翻译：公开了一种用于验证设计符合期望属性的方法，系统和计算机程序产品。该方法包括接收设计，设计的第一初始状态和关于设计的验证的属性。设计的第一初始状态被扩展以创建包含从设计的第一初始状态可访问的一个或多个状态的第一初始状态的超集。合成超集以定义设计的第二初始状态。超设计对设计的应用通过将切入点插入到超集中来获得修改后的超集，并且参考修改后的超集来验证该属性。

4. 发明申请

US20070074136A1 Using constraints in design verification 有权
标题翻译：在设计验证中使用约束
公开(公告)号：US20070074136A1
公开(公告)日：2007-03-29
申请号：US11236451
申请日：2005-09-27
申请人： Jason Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
发明人： Jason Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate abstraction (N′) of the netlist. A space state (S′) is created by enumerating the states of N′ from which the identified target may be asserted. A constraint space C′ is then derived from the state space S′, where C′ is the logical complement of S′. The process is repeated for multiple selected targets and the constraint spaces from each iteration are logically ANDed. Creating an overapproximate abstraction may include replacing a sequential gate with a random gate. Identifying a sequential gate may include selecting a target in the netlist, performing underapproximate verification of the target, and, if a spurious failure occurs, selecting a gate further down the fanin chain of the currently selected gate.
摘要翻译：一种用于生成用于验证集成电路设计的约束的方法包括识别设计的网表（N）中的目标并创建网表的过近似抽象（N'）。通过枚举从其识别出的目标可以被断言的N'的状态来创建空间状态（S'）。然后从状态空间S'导出约束空间C'，其中C'是S'的逻辑补码。对于多个选定的目标重复该过程，并且来自每个迭代的约束空间被逻辑地进行AND。创建过近似抽象可能包括用随机门替换顺序门。识别顺序门可以包括选择网表中的目标，执行目标的近似不正确的验证，并且如果发生虚假故障，则选择进一步向下沿当前选择的门的扇形链的门。

5. 发明授权

US07788615B2 Computer program product for verification using reachability overapproximation 失效
标题翻译：使用可达性过近似的验证计算机程序产品
公开(公告)号：US07788615B2
公开(公告)日：2010-08-31
申请号：US11938612
申请日：2007-11-12
申请人： Jason Raymond Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
发明人： Jason Raymond Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/504
摘要： A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is expanded to create a superset of the first initial state containing one or more states reachable from the first initial state of the design. A superset is synthesized to define a second initial state of the design. Application of the superset to the design is overapproximated through cutpoint insertion into the superset to obtain a modified superset, and the property is verified with reference to the modified superset.
摘要翻译：公开了一种用于验证设计符合期望属性的方法，系统和计算机程序产品。该方法包括接收设计，设计的第一初始状态和关于设计的验证的属性。设计的第一初始状态被扩展以创建包含从设计的第一初始状态可访问的一个或多个状态的第一初始状态的超集。合成超集以定义设计的第二初始状态。超设计对设计的应用通过将切入点插入到超集中来获得修改后的超集，并且参考修改后的超集来验证该属性。

6. 发明授权

US07856609B2 Using constraints in design verification 有权
标题翻译：在设计验证中使用约束
公开(公告)号：US07856609B2
公开(公告)日：2010-12-21
申请号：US12164781
申请日：2008-06-30
申请人： Jason R. Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
发明人： Jason R. Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/504
摘要： A method for generating a constraint for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate abstraction (N′) of the netlist. A space state (S′) is created by enumerating the states of N′ from which the identified target may be asserted. A constraint space C′ is then derived from the state space S′, where C′ is the logical complement of S′. The process is repeated for multiple selected targets and the constraint spaces from each iteration are logically ANDed. Creating an overapproximate abstraction may include replacing a sequential gate with a random gate. Identifying a sequential gate may include selecting a target in the netlist, performing underapproximate verification of the target, and, if a spurious failure occurs, selecting a gate further down the fanin chain of the currently selected gate.
摘要翻译：用于生成用于生成用于集成电路设计的验证的约束的约束的方法包括识别所述设计的网表（N）中的目标并且创建所述网表的过近似抽象（N'）。通过枚举从其识别出的目标可以被断言的N'的状态来创建空间状态（S'）。然后从状态空间S'导出约束空间C'，其中C'是S'的逻辑补码。对于多个选定的目标重复该过程，并且来自每个迭代的约束空间被逻辑地进行AND。创建过近似抽象可能包括用随机门替换顺序门。识别顺序门可以包括选择网表中的目标，执行目标的近似不正确的验证，并且如果发生虚假故障，则选择进一步向下沿当前选择的门的扇形链的门。

7. 发明授权

US07421669B2 Using constraints in design verification 有权
标题翻译：在设计验证中使用约束
公开(公告)号：US07421669B2
公开(公告)日：2008-09-02
申请号：US11236451
申请日：2005-09-27
申请人： Jason Raymond Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
发明人： Jason Raymond Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/504
摘要： A method for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate abstraction (N′) of the netlist. A space state (S′) is created by enumerating the states of N′ from which the identified target may be asserted. A constraint space C′ is then derived from the state space S′, where C′ is the logical complement of S′. The process is repeated for multiple selected targets and the constraint spaces from each iteration are logically ANDed. Creating an overapproximate abstraction may include replacing a sequential gate with a random gate. Identifying a sequential gate may include selecting a target in the netlist, performing underapproximate verification of the target, and, if a spurious failure occurs, selecting a gate further down the fanin chain of the currently selected gate.
摘要翻译：一种用于生成用于验证集成电路设计的约束的方法包括识别设计的网表（N）中的目标并创建网表的过近似抽象（N'）。通过枚举从其识别出的目标可以被断言的N'的状态来创建空间状态（S'）。然后从状态空间S'导出约束空间C'，其中C'是S'的逻辑补码。对于多个选定的目标重复该过程，并且来自每个迭代的约束空间被逻辑地进行AND。创建过近似抽象可能包括用随机门替换顺序门。识别顺序门可以包括选择网表中的目标，执行目标的近似不正确的验证，并且如果发生虚假故障，则选择进一步向下沿当前选择的门的扇形链的门。

8. 发明授权

US07322017B2 Method for verification using reachability overapproximation 有权
标题翻译：使用可达性过近似验证的方法
公开(公告)号：US07322017B2
公开(公告)日：2008-01-22
申请号：US11011245
申请日：2004-12-14
申请人： Jason Raymond Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
发明人： Jason Raymond Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/504
摘要： A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is expanded to create a superset of the first initial state containing one or more states reachable from the first initial state of the design. A superset is synthesized to define a second initial state of the design. Application of the superset to the design is overapproximated through cutpoint insertion into the superset to obtain a modified superset, and the property is verified with reference to the modified superset.
摘要翻译：公开了一种用于验证设计符合期望属性的方法，系统和计算机程序产品。该方法包括接收设计，设计的第一初始状态和关于设计的验证的属性。设计的第一初始状态被扩展以创建包含从设计的第一初始状态可访问的一个或多个状态的第一初始状态的超集。合成超集以定义设计的第二初始状态。超设计对设计的应用通过将切入点插入到超集中来获得修改后的超集，并且参考修改后的超集来验证该属性。

9. 发明授权

US07475370B2 System for verification using reachability overapproximation 失效
标题翻译：使用可达性过近似验证的系统
公开(公告)号：US07475370B2
公开(公告)日：2009-01-06
申请号：US11938656
申请日：2007-11-12
申请人： Jason Raymond Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
发明人： Jason Raymond Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/504
摘要： A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is expanded to create a superset of the first initial state containing one or more states reachable from the first initial state of the design. A superset is synthesized to define a second initial state of the design. Application of the superset to the design is overapproximated through cutpoint insertion into the superset to obtain a modified superset, and the property is verified with reference to the modified superset.
摘要翻译：公开了一种用于验证设计符合期望属性的方法，系统和计算机程序产品。该方法包括接收设计，设计的第一初始状态和关于设计的验证的属性。设计的第一初始状态被扩展以创建包含从设计的第一初始状态可访问的一个或多个状态的第一初始状态的超集。合成超集以定义设计的第二初始状态。超设计对设计的应用通过将切入点插入到超集中来获得修改后的超集，并且参考修改后的超集来验证该属性。

10. 发明申请

US20080256499A1 USING CONSTRAINTS IN DESIGN VERIFICATION 有权
标题翻译：在设计验证中使用约束
公开(公告)号：US20080256499A1
公开(公告)日：2008-10-16
申请号：US12164781
申请日：2008-06-30
申请人： Jason Raymond Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
发明人： Jason Raymond Baumgartner , Hari Mony , Viresh Paruthi , Jiazhao Xu
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for generating a constraint for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate abstraction (N′) of the netlist. A space state (S′) is created by enumerating the states of N′ from which the identified target may be asserted. A constraint space C′ is then derived from the state space S′, where C′ is the logical complement of S′. The process is repeated for multiple selected targets and the constraint spaces from each iteration are logically ANDed. Creating an overapproximate abstraction may include replacing a sequential gate with a random gate. Identifying a sequential gate may include selecting a target in the netlist, performing underapproximate verification of the target, and, if a spurious failure occurs, selecting a gate further down the fanin chain of the currently selected gate.
摘要翻译：用于生成用于生成用于集成电路设计的验证的约束的约束的方法包括识别所述设计的网表（N）中的目标并且创建所述网表的过近似抽象（N'）。通过枚举从其识别出的目标可以被断言的N'的状态来创建空间状态（S'）。然后从状态空间S'导出约束空间C'，其中C'是S'的逻辑补码。对于多个选定的目标重复该过程，并且来自每个迭代的约束空间被逻辑地进行AND。创建过近似抽象可能包括用随机门替换顺序门。识别顺序门可以包括选择网表中的目标，执行目标的近似不正确的验证，并且如果发生虚假故障，则选择进一步向下沿当前选择的门的扇形链的门。

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