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1. 发明授权

US10469979B2 Managing data access in mobile devices 有权
公开(公告)号：US10469979B2
公开(公告)日：2019-11-05
申请号：US13459779
申请日：2012-04-30
申请人： Patrick Joseph Bohrer , Ahmed Gheith , James Lyle Peterson
发明人： Patrick Joseph Bohrer , Ahmed Gheith , James Lyle Peterson
IPC分类号： G06F15/16 , H04W4/00
摘要： A method for managing data access in a mobile device is provided in the illustrative embodiments. Using a data manager executing in the mobile device, a data item is configured in a data model. A value parameter of the data item is populated with data and a status parameter of the data item is populated with a status indication. A subscription to the data item is received from a mobile application executing in the mobile device. In response to the subscription, the data and the status of the data item are sent to the mobile application.

2. 发明授权

US07020700B1 Client side socks server for an internet client 失效
标题翻译：客户端袜子服务器为互联网客户端
公开(公告)号：US07020700B1
公开(公告)日：2006-03-28
申请号：US08808286
申请日：1997-02-28
申请人： Craig Alan Bennett , Christian Lita , James Lyle Peterson , Joseph Raymond Thompson
发明人： Craig Alan Bennett , Christian Lita , James Lyle Peterson , Joseph Raymond Thompson
IPC分类号： G06F15/173
CPC分类号： H04L67/22 , H04L63/0281 , H04L67/28 , H04L67/289 , H04L69/16 , H04L69/162 , H04L69/168 , H04L69/32
摘要： An Internet client is provided with a SOCKS server. The client comprises a processor having an operating system, and a suite of one or more Internet tools. The SOCKS proxy server includes means for intercepting and servicing connection requests from the Internet tools. Preferably, the proxy server has a predetermined Internet Protocol address, preferably the loopback address. If the loopback address is not available on the protocol stack, a redirecting mechanism is used to redirect connection requests associated with stale IP addresses to a current IP address. The SOCKS server includes a filtering mechanism for filtering connection requests to particular servers, and a monitoring mechanism for monitoring network IP activity.
摘要翻译：一个互联网客户端提供了一个SOCKS服务器。客户机包括具有操作系统的处理器和一个或多个互联网工具的套件。 SOCKS代理服务器包括用于拦截和维护来自Internet工具的连接请求的装置。优选地，代理服务器具有预定的因特网协议地址，优选地是环回地址。如果协议栈中的环回地址不可用，则使用重定向机制将与过期IP地址相关联的连接请求重定向到当前IP地址。 SOCKS服务器包括用于过滤对特定服务器的连接请求的过滤机制，以及用于监控网络IP活动的监视机制。

3. 发明授权

US08417913B2 Superpage coalescing which supports read/write access to a new virtual superpage mapping during copying of physical pages 失效
标题翻译： Superpage coalescing在复制物理页面期间支持对新的虚拟超级页面映射的读/写访问
公开(公告)号：US08417913B2
公开(公告)日：2013-04-09
申请号：US10713733
申请日：2003-11-13
申请人： Elmootazbellah Nabil Elnozahy , James Lyle Peterson , Ramakrishnan Rajamony , Hazim Shafi
发明人： Elmootazbellah Nabil Elnozahy , James Lyle Peterson , Ramakrishnan Rajamony , Hazim Shafi
IPC分类号： G06F12/00
CPC分类号： G06F12/1045
摘要： A method of assigning virtual memory to physical memory in a data processing system allocates a set of contiguous physical memory pages for a new page mapping, instructs the memory controller to move the virtual memory pages according to the new page mapping, and then allows access to the virtual memory pages using the new page mapping while the memory controller is still copying the virtual memory pages to the set of physical memory pages. The memory controller can use a mapping table which temporarily stores entries of the old and new page addresses, and releases the entries as copying for each entry is completed. The translation lookaside buffer (TLB) entries in the processor cores are updated for the new page addresses prior to completion of copying of the memory pages by the memory controller. The invention can be extended to non-uniform memory array (NUMA) systems. For systems with cache memory, any cache entry which is affected by the page move can be updated by modifying its address tag according to the new page mapping. This tag modification may be limited to cache entries in a dirty coherency state. The cache can further relocate a cache entry based on a changed congruence class for any modified address tag.
摘要翻译：将虚拟存储器分配给数据处理系统中的物理存储器的方法为新的页面映射分配一组连续的物理存储器页面，指示存储器控制器根据新的页面映射移动虚拟存储器页面，然后允许访问虚拟内存页面使用新页面映射，而内存控制器仍将虚拟内存页面复制到物理内存页面集合。存储器控制器可以使用临时存储旧页面地址和新页面地址的条目的映射表，并且对于每个条目的拷贝完成，释放条目。在由存储器控制器完成对存储器页面的复制之前，处理器核心中的翻译后备缓冲器（TLB）条目针对新的页地址进行更新。本发明可以扩展到非均匀存储器阵列（NUMA）系统。对于具有缓存内存的系统，可以通过根据新页面映射修改其地址标签来更新受页面移动影响的任何缓存条目。该标签修改可能被限制在脏相关性状态下的高速缓存条目。高速缓存可以根据修改后的地址标签的改变的一致性类别进一步重新定位缓存条目。

4. 发明申请

US20110296423A1 FRAMEWORK FOR SCHEDULING MULTICORE PROCESSORS 有权
标题翻译：调度多处理器的框架
公开(公告)号：US20110296423A1
公开(公告)日：2011-12-01
申请号：US12789015
申请日：2010-05-27
申请人： ELMOOTAZBELLAH NABIL ELNOZAHY , Heather Lynn Hanson , James Lyle Peterson , Freeman Leigh Rawson, III , Malcolm Scott Ware
发明人： ELMOOTAZBELLAH NABIL ELNOZAHY , Heather Lynn Hanson , James Lyle Peterson , Freeman Leigh Rawson, III , Malcolm Scott Ware
IPC分类号： G06F9/46
CPC分类号： G06F9/4893 , G06F9/4881 , G06F9/5027 , G06F9/54 , Y02D10/22 , Y02D10/24
摘要： A method, system, and computer usable program product for a framework for scheduling tasks in a multi-core processor or multiprocessor system are provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi-core processor.
摘要翻译：在说明性实施例中提供了用于在多核处理器或多处理器系统中调度任务的框架的方法，系统和计算机可用程序产品。根据调度规则中的顺序选择线程，该线程是在数据处理系统中执行的应用程序的线程，线程形成一束线程中的引导线程。一组核心属性中的核心属性的值根据与引导线程相关联的一组线程属性中的相应线程属性来确定。确定是否可以将第二线程添加到捆绑包，使得包括第二线程的包将满足策略。如果确定是肯定的，则将第二个线程添加到捆绑包中。该捆绑计划使用多核处理器的核心进行执行。

5. 发明授权

US07080214B2 Directory based support for function shipping in a multiprocessor system 失效
标题翻译：基于目录的多处理器系统中功能运输的支持
公开(公告)号：US07080214B2
公开(公告)日：2006-07-18
申请号：US10687261
申请日：2003-10-16
申请人： James Lyle Peterson , Ramakrishnan Rajamony , Hazim Shafi
发明人： James Lyle Peterson , Ramakrishnan Rajamony , Hazim Shafi
IPC分类号： G06F12/08
CPC分类号： G06F12/0813 , G06F12/0817
摘要： A multiprocessor system includes a plurality of data processing nodes. Each node has a processor coupled to a system memory, a cache memory, and a cache directory. The cache directory contains cache coherency information for a predetermined range of system memory addresses. An interconnection enables the nodes to exchange messages. A node initiating a function shipping request identifies an intermediate destination directory based on a list of the function's operands and sends a message indicating the function and its corresponding operands to the identified destination directory. The destination cache directory determines a target node based, at least in part, on its cache coherency status information to reduce memory access latency by selecting a target node where all or some of the operands are valid in the local cache memory. The destination directory then ships the function to the target node over the interconnection.
摘要翻译：多处理器系统包括多个数据处理节点。每个节点具有耦合到系统存储器，高速缓存存储器和高速缓存目录的处理器。缓存目录包含用于系统存储器地址的预定范围的高速缓存一致性信息。互连使得节点能够交换消息。启动功能运送请求的节点基于功能的操作数的列表来识别中间目的地目录，并将指示该功能及其对应的操作数的消息发送到所识别的目的地目录。目的地缓存目录至少部分地基于其高速缓存一致性状态信息来确定目标节点，以通过选择其中全部或某些操作数在本地高速缓冲存储器中有效的目标节点来减少存储器访问等待时间。目的地目录然后通过互连将功能发送到目标节点。

6. 发明授权

US06708181B1 System and method for initializing variables in an object-oriented program 失效
标题翻译：用于在面向对象程序中初始化变量的系统和方法
公开(公告)号：US06708181B1
公开(公告)日：2004-03-16
申请号：US09145102
申请日：1998-09-01
申请人： James Lyle Peterson
发明人： James Lyle Peterson
IPC分类号： G06F1730
CPC分类号： G06F9/445 , G06F9/4488 , Y10S707/99944 , Y10S707/99945
摘要： A method for initializing variables within class objects in a statically loaded object-oriented programming language. A two-phase flooding algorithm is utilized to initialize the core variables within each class along with those variables needed to be initialized before the core variables. An initialization algorithm is performed within each of the class objects in a recursive manner. Once a class object has begun the initialization process internally, calls to again begin the initialization process within that class object from another class object will result in a return in order to prevent duplicates of the initialization process from being performed within each of the class objects.
摘要翻译：在静态加载的面向对象编程语言中初始化类对象中的变量的方法。利用两相淹没算法来初始化每个类中的核心变量以及在核心变量之前需要初始化的变量。以递归方式在每个类对象内执行初始化算法。一旦类对象已经在内部开始初始化过程，调用再次开始来自另一个类对象的类对象中的初始化过程将导致返回，以防止在每个类对象内执行初始化过程的重复。

7. 发明授权

US08990831B2 Framework for scheduling multicore processors 有权
标题翻译：多核处理器调度框架
公开(公告)号：US08990831B2
公开(公告)日：2015-03-24
申请号：US13413768
申请日：2012-03-07
申请人： Elmootazbellah Nabil Elnozahy , Heather Lynn Hanson , James Lyle Peterson , Freeman Leigh Rawson, III , Malcolm Scott Ware
发明人： Elmootazbellah Nabil Elnozahy , Heather Lynn Hanson , James Lyle Peterson , Freeman Leigh Rawson, III , Malcolm Scott Ware
IPC分类号： G06F3/00 , G06F9/46 , G06F9/48 , G06F9/54 , G06F9/50
CPC分类号： G06F9/4893 , G06F9/4881 , G06F9/5027 , G06F9/54 , Y02D10/22 , Y02D10/24
摘要： A method for a framework for scheduling tasks in a multi-core processor or multiprocessor system is provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi-core processor.
摘要翻译：在说明性实施例中提供了用于在多核处理器或多处理器系统中调度任务的框架的方法。根据调度规则中的顺序选择线程，该线程是在数据处理系统中执行的应用程序的线程，线程形成一束线程中的引导线程。一组核心属性中的核心属性的值根据与引导线程相关联的一组线程属性中的相应线程属性来确定。确定是否可以将第二线程添加到捆绑包，使得包括第二线程的包将满足策略。如果确定是肯定的，则将第二个线程添加到捆绑包中。该捆绑计划使用多核处理器的核心进行执行。

8. 发明授权

US08510749B2 Framework for scheduling multicore processors 有权
标题翻译：多核处理器调度框架
公开(公告)号：US08510749B2
公开(公告)日：2013-08-13
申请号：US12789015
申请日：2010-05-27
申请人： Elmootazbellah Nabil Elnozahy , Heather Lynn Hanson , James Lyle Peterson , Freeman Leigh Rawson, III , Malcolm Scott Ware
发明人： Elmootazbellah Nabil Elnozahy , Heather Lynn Hanson , James Lyle Peterson , Freeman Leigh Rawson, III , Malcolm Scott Ware
IPC分类号： G06F3/00 , G06F9/46
CPC分类号： G06F9/4893 , G06F9/4881 , G06F9/5027 , G06F9/54 , Y02D10/22 , Y02D10/24
摘要： A system, and computer usable program product for a framework for scheduling tasks in a multi-core processor or multiprocessor system are provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi-core processor.
摘要翻译：在说明性实施例中提供了用于在多核处理器或多处理器系统中调度任务的框架的系统和计算机可用程序产品。根据调度规则中的顺序选择线程，该线程是在数据处理系统中执行的应用程序的线程，线程形成一束线程中的引导线程。一组核心属性中的核心属性的值根据与引导线程相关联的一组线程属性中的相应线程属性来确定。确定是否可以将第二线程添加到捆绑包，使得包括第二线程的包将满足策略。如果确定是肯定的，则将第二个线程添加到捆绑包中。该捆绑计划使用多核处理器的核心进行执行。

9. 发明授权

US06421775B1 Interconnected processing nodes configurable as at least one non-uniform memory access (NUMA) data processing system 有权
标题翻译：互连处理节点可配置为至少一个非均匀存储器访问（NUMA）数据处理系统
公开(公告)号：US06421775B1
公开(公告)日：2002-07-16
申请号：US09335301
申请日：1999-06-17
申请人： Bishop Chapman Brock , David Brian Glasco , James Lyle Peterson , Ramakrishnan Rajamony , Ronald Lynn Rockhold
发明人： Bishop Chapman Brock , David Brian Glasco , James Lyle Peterson , Ramakrishnan Rajamony , Ronald Lynn Rockhold
IPC分类号： G06F15177
CPC分类号： G06F15/177
摘要： A data processing system includes a plurality of processing nodes that each contain at least one processor and data storage. The plurality of processing nodes are coupled together by a system interconnect. The data processing system further includes a configuration utility residing in data storage within at least one of the plurality of processing nodes. The configuration utility selectively configures the plurality of processing nodes into either a single non-uniform memory access (NUMA) system or into multiple independent data processing systems through communication via the system interconnect.
摘要翻译：数据处理系统包括多个处理节点，每个处理节点包含至少一个处理器和数据存储器。多个处理节点通过系统互连耦合在一起。数据处理系统还包括驻留在多个处理节点中的至少一个处理节点内的数据存储器中的配置实用程序。配置实用程序通过经由系统互连的通信将多个处理节点选择性地配置为单个非均匀存储器访问（NUMA）系统或多个独立的数据处理系统。

10. 发明授权

US07231509B2 Extended register bank allocation based on status mask bits set by allocation instruction for respective code block 失效
标题翻译：基于由各个代码块的分配指令设置的状态屏蔽位的扩展寄存器组分配
公开(公告)号：US07231509B2
公开(公告)日：2007-06-12
申请号：US11034559
申请日：2005-01-13
申请人： Ahmed Gheith , James Lyle Peterson , Richard Ormond Simpson
发明人： Ahmed Gheith , James Lyle Peterson , Richard Ormond Simpson
IPC分类号： G06F9/34
CPC分类号： G06F9/30181 , G06F9/30076 , G06F9/30098 , G06F9/3012 , G06F9/30138 , G06F9/3836 , G06F9/384
摘要： An extended register processor includes a register file having a legacy register set and an extended register set. The extended register set includes a plurality of extended registers accessible only to extended register instructions. The processor maps extended register references to physical extended registers at run time. The processor includes a configurable extended register mapping unit to support this functionality. The mapping unit is accessible to an instruction decoder, which detects extended register references and forwards them to the mapping unit. The mapping unit returns a physical extended register corresponding to the extended register reference in the instruction. The mapping unit is configurable so that, for example, the mapping is specific to a code block. An extended register allocation instruction causes the processor to allocate a portion of the extended register set to the code block in which the declaration is located and to configure the mapping unit to reflect the allocation.
摘要翻译：扩展寄存器处理器包括具有遗留寄存器组和扩展寄存器组的寄存器文件。扩展寄存器集合包括可扩展寄存器指令可访问的多个扩展寄存器。处理器在运行时将扩展寄存器引用映射到物理扩展寄存器。该处理器包括一个可配置的扩展寄存器映射单元来支持该功能。指令解码器可访问映射单元，该指令解码器检测扩展寄存器引用并将其转发给映射单元。映射单元返回与指令中的扩展寄存器引用相对应的物理扩展寄存器。映射单元是可配置的，使得例如映射特定于代码块。扩展寄存器分配指令使处理器将扩展寄存器集的一部分分配给声明所在的代码块，并配置映射单元以反映分配。

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