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1. 发明授权

US08330548B2 Latched ring oscillator device for on-chip measurement of clock to output delay in a latch 有权
标题翻译：锁存环形振荡器器件，用于片内测量时钟以在锁存器中输出延迟
公开(公告)号：US08330548B2
公开(公告)日：2012-12-11
申请号：US12860143
申请日：2010-08-20
申请人： Israel A. Wagner
发明人： Israel A. Wagner
IPC分类号： H03K3/03
CPC分类号： H03K3/0315
摘要： A novel and useful apparatus and related method for on-chip measurement of the clock to output delay of a latch within an integrated circuit. The delay measurement mechanism enables measuring the time delay from the transition of the clock input to the data output of a latch. The output delay of the on-chip latch is measured by making the latch delay part of a ring oscillator and measuring its frequency of oscillation. A latch based delay stage is used to construct the ring oscillator in which a delayed short pulse derived from the input edge is used as the trigger for the latch. The latched ring oscillator mechanism of the invention can be used to measure the clock to output (C2Q) delay of on-chip latch devices.
摘要翻译：一种用于片内测量时钟以输出集成电路内的锁存器的延迟的新颖有用的装置和相关方法。延迟测量机制能够测量从时钟输入到锁存器的数据输出的转换的时间延迟。通过使环形振荡器的锁存延迟部分并测量其振荡频率来测量片上锁存器的输出延迟。基于锁存器的延迟级用于构造环形振荡器，其中从输入边缘导出的延迟短脉冲用作锁存器的触发器。本发明的锁存环形振荡器机构可用于测量片上锁存器件的时钟输出（C2Q）延迟。

2. 发明授权

US08161427B2 Logic circuit and method of logic circuit design 有权
标题翻译：逻辑电路和逻辑电路设计方法
公开(公告)号：US08161427B2
公开(公告)日：2012-04-17
申请号：US12758072
申请日：2010-04-12
申请人： Arkadiy Morgenshtein , Alexander Fish , Israel A. Wagner
发明人： Arkadiy Morgenshtein , Alexander Fish , Israel A. Wagner
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , H03K19/0948
摘要： A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The p-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor network is connected to the first dedicated logic terminal, and the first network gate connection of the p-type transistor network is connected to the first logic input. The second logic block consists of a network of n-type transistors which implements a logic function complementary to the logic function implemented by the first logic block. The n-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the n-type transistor network is connected to the second dedicated logic terminal, and the first network gate connection of the n-type transistor network is connected to the second logic input. The inner diffusion connections of the p-type network and of the n-type network are connected together to form a common diffusion logic terminal.
摘要翻译：互补逻辑电路包括第一逻辑输入，第二逻辑输入，第一专用逻辑终端，第二专用逻辑终端，第一逻辑块和第二逻辑块。第一逻辑块由用于实现预定逻辑功能的p型晶体管的网络组成。 p型晶体管网络具有外部扩散连接，第一网络栅极连接和内部扩散连接。 p型晶体管网络的外部扩散连接连接到第一专用逻辑端子，p型晶体管网络的第一网络连接连接到第一逻辑输入端。第二逻辑块由n型晶体管的网络组成，其实现与由第一逻辑块实现的逻辑功能互补的逻辑功能。 n型晶体管网络具有外部扩散连接，第一网络栅极连接和内部扩散连接。 n型晶体管网络的外部扩散连接连接到第二专用逻辑端子，并且n型晶体管网络的第一网络栅极连接连接到第二逻辑输入端。 p型网络和n型网络的内部扩散连接被连接在一起形成一个共同的扩散逻辑终端。

3. 发明授权

US07825693B1 Reduced duty cycle distortion using controlled body device 失效
标题翻译：使用受控体设备减少占空比失真
公开(公告)号：US07825693B1
公开(公告)日：2010-11-02
申请号：US12550877
申请日：2009-08-31
申请人： Oded Katz , Israel A. Wagner
发明人： Oded Katz , Israel A. Wagner
IPC分类号： H03K19/094
CPC分类号： H03K5/1565
摘要： A semiconductor chip comprising a reference circuit and a target circuit. The reference circuit comprises a first P-channel field effect transistor (PFET) and a first N-channel field effect transistor (NFET). A reference voltage is connected to gates of the first PFET and first NFET. A body control voltage node is formed by connecting a drain of the first PFET, a body of the first PFET, a drain of the first NFET and a body of the first NFET. A target circuit comprises a second PFET and a second NFET. The body control voltage node is connected to a body of the second PFET and the second NFET. The body control voltage improves duty cycle in the target circuit compared to a similarly designed circuit having PFET bodies connected to Vdd and NFET bodies connected to Ground.
摘要翻译：一种包括参考电路和目标电路的半导体芯片。参考电路包括第一P沟道场效应晶体管（PFET）和第一N沟道场效应晶体管（NFET）。参考电压连接到第一PFET和第一NFET的栅极。通过连接第一PFET的漏极，第一PFET的主体，第一NFET的漏极和第一NFET的主体来形成主体控制电压节点。目标电路包括第二PFET和第二NFET。身体控制电压节点连接到第二PFET和第二NFET的主体。与具有连接到连接到地的Vdd和NFET主体的PFET体的类似设计的电路相比，身体控制电压改善了目标电路中的占空比。

4. 发明申请

US20120044024A1 LATCHED RING OSCILLATOR DEVICE FOR ON-CHIP MEASUREMENT OF CLOCK TO OUTPUT DELAY IN A LATCH 有权
标题翻译：用于片上测量时钟到锁存器中的输出延迟的锁定环振荡器装置
公开(公告)号：US20120044024A1
公开(公告)日：2012-02-23
申请号：US12860143
申请日：2010-08-20
申请人： Israel A. WAGNER
发明人： Israel A. WAGNER
IPC分类号： H03K3/03
CPC分类号： H03K3/0315
摘要： A novel and useful apparatus and related method for on-chip measurement of the clock to output delay of a latch within an integrated circuit. The delay measurement mechanism enables measuring the time delay from the transition of the clock input to the data output of a latch. The output delay of the on-chip latch is measured by making the latch delay part of a ring oscillator and measuring its frequency of oscillation. A latch based delay stage is used to construct the ring oscillator in which a delayed short pulse derived from the input edge is used as the trigger for the latch. The latched ring oscillator mechanism of the invention can be used to measure the clock to output (C2Q) delay of on-chip latch devices.
摘要翻译：一种用于片内测量时钟以输出集成电路内的锁存器的延迟的新颖且有用的装置和相关方法。延迟测量机制能够测量从时钟输入到锁存器的数据输出的转换的时间延迟。通过使环形振荡器的锁存延迟部分并测量其振荡频率来测量片上锁存器的输出延迟。基于锁存器的延迟级用于构造环形振荡器，其中从输入边缘导出的延迟短脉冲用作锁存器的触发器。本发明的锁存环形振荡器机构可用于测量片上锁存器件的时钟输出（C2Q）延迟。

5. 发明授权

US07994846B2 Method and mechanism to reduce current variation in a current reference branch circuit 失效
标题翻译：减小电流参考分支电路中电流变化的方法和机制
公开(公告)号：US07994846B2
公开(公告)日：2011-08-09
申请号：US12465941
申请日：2009-05-14
申请人： Oded Katz , Israel A. Wagner
发明人： Oded Katz , Israel A. Wagner
IPC分类号： G05F3/24
CPC分类号： G05F3/205 , G05F3/262
摘要： A feedback mechanism to reduce current variation observed in a current reference branch circuit by using body voltage control to compensate process, temperature and supply voltage variations. The current reference output voltage, which is proportional to the reference current, is sampled into a feedback loop, which controls the field effect transistor body voltage. The method and mechanism uses Corner Robust Current Reference in order to keep the design simple and diminish variation between Process Voltage Temperature (PVT) corners. This method exhibits small variation in the reference current magnitude.
摘要翻译：一种反馈机制，用于通过使用体电压控制来补偿电流参考分支电路中观察到的电流变化，以补偿过程，温度和电源电压变化。与参考电流成比例的电流参考输出电压被采样到反馈环路中，该反馈环路控制场效应晶体管体电压。该方法和机制使用角坚固电流参考，以保持设计简单和减少过程电压温度（PVT）角之间的变化。该方法在参考电流幅度方面表现出小的变化。

6. 发明授权

US07962539B2 System, method and device of generating a random value 失效
标题翻译：生成随机值的系统，方法和设备
公开(公告)号：US07962539B2
公开(公告)日：2011-06-14
申请号：US11742002
申请日：2007-04-30
申请人： Assaf Barak , Eli Bloch , Elazar Kachir , Anastasia Ester Kapchits , Oded Katz , Moshe Leibowitz , Dan Ramon , Israel A. Wagner
发明人： Assaf Barak , Eli Bloch , Elazar Kachir , Anastasia Ester Kapchits , Oded Katz , Moshe Leibowitz , Dan Ramon , Israel A. Wagner
IPC分类号： G06F1/02
CPC分类号： G06F7/588
摘要： Some demonstrative embodiments of the invention include a method, apparatus and system of generating a random number. A random number generator may include, for example, a plurality of different random-number-generation modules adapted to generate random bits at a plurality of bit paths; and a combiner adapted to combine the bits of the plurality of paths. Other embodiments are described and claimed.
摘要翻译：本发明的一些演示实施例包括产生随机数的方法，装置和系统。随机数生成器可以包括例如适于在多个位路径处生成随机位的多个不同的随机数生成模块; 以及适于组合多个路径的比特的组合器。描述和要求保护其他实施例。

7. 发明授权

US07941471B2 Differential approach to current-mode chaos based random number generator 有权
标题翻译：基于当前模式混沌的随机数发生器的差分方法
公开(公告)号：US07941471B2
公开(公告)日：2011-05-10
申请号：US11668130
申请日：2007-01-29
申请人： Oded Katz , Dan Ramon , Israel A. Wagner
发明人： Oded Katz , Dan Ramon , Israel A. Wagner
IPC分类号： G06F1/02
CPC分类号： G06F7/588 , H04L9/001
摘要： Disclosed is method and chaos circuit for a random number generator comprising: a differential sample and hold circuit portion having a first and a second differential signal input and a first and a second differential signal output, a differential non-linear discriminator circuit portion that applies a differential discrimination function upon the first and the second differential signal output and outputs a first and a second discriminated signal, where the first and the second discriminated signals are also coupled to the first and the second differential signal inputs via a first and a second loop feedback.
摘要翻译：公开了一种随机数发生器的方法和混沌电路，包括：差分采样和保持电路部分，具有第一和第二差分信号输入和第一和第二差分信号输出;差分非线性鉴别器电路部分，差分鉴别功能在第一和第二差分信号输出端输出并输出第一和第二鉴别信号，其中第一和第二鉴别信号也经由第一和第二环路反馈耦合到第一和第二差分信号输入。

8. 发明申请

US20120126853A1 LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN 审中-公开
标题翻译：逻辑电路和逻辑电路设计方法
公开(公告)号：US20120126853A1
公开(公告)日：2012-05-24
申请号：US13364355
申请日：2012-02-02
申请人： Arkadiy MORGENSHTEIN , Alexander Fish , Israel A. Wagner
发明人： Arkadiy MORGENSHTEIN , Alexander Fish , Israel A. Wagner
IPC分类号： H03K19/0948
CPC分类号： G06F17/505 , H03K19/0948
摘要： A complementary logic circuit, comprising: a first and second logic input; a first and second dedicated logic terminal; a p-type transistor network comprising multiple p-type transistors, for implementing a predetermined logic function, and having an outer diffusion connection connected to the first dedicated logic terminal, a first network gate connection connected to the first logic input, and an inner diffusion connection; and an n-type transistor network comprising multiple n-type transistors, for implementing a logic function complementary to the predetermined logic function, and having an outer diffusion connection connected to the second dedicated logic terminal, a first network gate connection connected to the second logic input, and an inner diffusion connection; the inner diffusion connections of the p-type transistor network and of the n-type transistor network being connected to form a common diffusion logic terminal.
摘要翻译：一种互补逻辑电路，包括：第一和第二逻辑输入; 第一和第二专用逻辑终端; 包括多个p型晶体管的p型晶体管网络，用于实现预定的逻辑功能，并且具有连接到第一专用逻辑端子的外部扩散连接，连接到第一逻辑输入的第一网络栅极连接和内部扩散连接; 以及包括多个n型晶体管的n型晶体管网络，用于实现与所述预定逻辑功能互补的逻辑功能，并且具有连接到所述第二专用逻辑端子的外部扩散连接，连接到所述第二逻辑电路的第一网络栅极连接输入和内部扩散连接; p型晶体管网络和n型晶体管网络的内部扩散连接被连接以形成公共扩散逻辑端子。

9. 发明申请

US20100289563A1 Method and Mechanism to Reduce Current Variation in a Current Reference Branch Circuit 失效
标题翻译：减少电流参考分支电路中电流变化的方法和机制
公开(公告)号：US20100289563A1
公开(公告)日：2010-11-18
申请号：US12465941
申请日：2009-05-14
申请人： Oded Katz , Israel A. Wagner
发明人： Oded Katz , Israel A. Wagner
IPC分类号： G05F1/10
CPC分类号： G05F3/205 , G05F3/262
摘要： A novel and useful system and method of providing a feedback mechanism to reduce current variation observed in a current reference branch circuit by using body voltage control to compensate process, temperature and supply voltage variations. The current reference output voltage, which is proportional to the reference current, is sampled into a feedback loop, which controls the field effect transistor body voltage. The method and mechanism of the present invention uses Corner Robust Current Reference in order to keep the design simple and diminish variation between Process Voltage Temperature (PVT) corners. This method exhibits superior robustness with smaller variation in the reference current magnitude.
摘要翻译：一种新颖有用的系统和方法，通过使用体电压控制来补偿过程，温度和电源电压变化，提供反馈机制以减小在电流参考分支电路中观察到的电流变化。与参考电流成比例的电流参考输出电压被采样到反馈环路中，该反馈环路控制场效应晶体管体电压。本发明的方法和机理使用角坚固电流参考，以保持设计简单和减少过程电压温度（PVT）角之间的变化。该方法表现出优异的鲁棒性，而参考电流幅度的变化较小。

10. 发明申请

US20100194439A1 LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN 有权
标题翻译：逻辑电路和逻辑电路设计方法
公开(公告)号：US20100194439A1
公开(公告)日：2010-08-05
申请号：US12758072
申请日：2010-04-12
申请人： Arkadiy MORGENSHTEIN , Alexander Fish , Israel A. Wagner
发明人： Arkadiy MORGENSHTEIN , Alexander Fish , Israel A. Wagner
IPC分类号： H03K19/094
CPC分类号： G06F17/505 , H03K19/0948
摘要： A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The p-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor network is connected to the first dedicated logic terminal, and the first network gate connection of the p-type transistor network is connected to the first logic input. The second logic block consists of a network of n-type transistors which implements a logic function complementary to the logic function implemented by the first logic block. The n-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the n-type transistor network is connected to the second dedicated logic terminal, and the first network gate connection of the n-type transistor network is connected to the second logic input. The inner diffusion connections of the p-type network and of the n-type network are connected together to form a common diffusion logic terminal.
摘要翻译：互补逻辑电路包括第一逻辑输入，第二逻辑输入，第一专用逻辑终端，第二专用逻辑终端，第一逻辑块和第二逻辑块。第一逻辑块由用于实现预定逻辑功能的p型晶体管的网络组成。 p型晶体管网络具有外部扩散连接，第一网络栅极连接和内部扩散连接。 p型晶体管网络的外部扩散连接连接到第一专用逻辑端子，p型晶体管网络的第一网络连接连接到第一逻辑输入端。第二逻辑块由n型晶体管的网络组成，其实现与由第一逻辑块实现的逻辑功能互补的逻辑功能。 n型晶体管网络具有外部扩散连接，第一网络栅极连接和内部扩散连接。 n型晶体管网络的外部扩散连接连接到第二专用逻辑端子，并且n型晶体管网络的第一网络栅极连接连接到第二逻辑输入端。 p型网络和n型网络的内部扩散连接被连接在一起形成一个共同的扩散逻辑终端。

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