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    • 2. 发明授权
    • Method for fabricating metal oxide semiconductor field effect transistor
    • 制造金属氧化物半导体场效应晶体管的方法
    • US5940710A
    • 1999-08-17
    • US610887
    • 1996-03-05
    • In Sool ChungYoung Tag Woo
    • In Sool ChungYoung Tag Woo
    • H01L21/335H01L21/336H01L29/10
    • H01L29/66575H01L29/1045H01L29/1083H01L29/66659
    • A method for fabricating a metal oxide semiconductor field effect transistor wherein source/drain junctions are formed by depositing and etching an oxide film having a desired thickness prior to the formation of a pocket region carried out by a pocket ion implantation after forming a gate oxide film and gate electrode on a channel region formed by implanting impurity ions in a silicon substrate. The pocket region is formed by impurity ions in source/drain regions exposed by etching the oxide film. Accordingly, it is possible to reduce the thermal budget applied to the source/drain junctions. As a result, the lateral diffusion of the impurity ions implanted in the source/drain junctions can be suppressed as much as possible. That is, the transistor fabricated in accordance with the present invention has a channel length longer than that obtained in accordance with the prior art. Accordingly, the transistor can have a highly compact or densely integrated size. Since source/drain electrodes are separately formed from each other in accordance with the present invention, the insulation between the source/drain electrodes can be effectively obtained.
    • 一种用于制造金属氧化物半导体场效应晶体管的方法,其中通过在形成栅极氧化膜之后通过口袋离子注入形成袋状区域之后沉积和蚀刻具有所需厚度的氧化膜形成源极/漏极结 以及通过在硅衬底中注入杂质离子形成的沟道区上的栅电极。 通过蚀刻氧化膜而暴露的源极/漏极区域中的杂质离子形成口袋区域。 因此,可以减少施加到源极/漏极结的热量预算。 结果,可以尽可能地抑制注入在源极/漏极结中的杂质离子的横向扩散。 也就是说,根据本发明制造的晶体管具有比根据现有技术获得的晶体管长度的沟道长度。 因此,晶体管可以具有高度紧凑或密集集成的尺寸。 由于源/漏电极根据本发明彼此分开形成,所以可以有效地获得源/漏电极之间的绝缘。
    • 4. 发明授权
    • DRAM with reduced leakage current
    • DRAM具有降低的漏电流
    • US5751653A
    • 1998-05-12
    • US867455
    • 1997-06-02
    • In Sool ChungJae Jin Lee
    • In Sool ChungJae Jin Lee
    • G11C11/407G11C11/34G11C11/406G11C11/408G11C13/00
    • G11C11/4087G11C11/4085
    • A DRAM with reduced leakage current includes at least two line driving means for transmitting high potential to a line selected by an address signal externally input; a main power line for transmitting a power source voltage externally supplied; secondary power lines for transmitting the power source voltage to the respective line driving means; switching means respectively connected between the main power line and secondary power lines; block selection means for outputting a signal where two block selection addresses are logically combined, to each of the line driving means, in order to select and operate one of the line driving means; and switching control means for outputting a signal which controls each of the switching means through the logical combination of the output signal of the block selection means and a refresh operation mode signal.
    • 具有减小的漏电流的DRAM包括用于将高电位传输到由外部输入的地址信号选择的线路的至少两个线路驱动装置; 用于发送外部电源电压的主电力线; 用于将电源电压发送到各线路驱动装置的二次电力线路; 分别连接在主电力线和二次电力线之间的开关装置; 块选择装置,用于将两个块选择地址逻辑地组合的信号输出到每个线路驱动装置,以便选择和操作线路驱动装置之一; 以及切换控制装置,用于通过块选择装置的输出信号和刷新操作模式信号的逻辑组合输出控制每个切换装置的信号。