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1. 发明授权

US06791558B2 Method and apparatus for processing pixel rasterization in three-dimensional rendering processor 有权
标题翻译：在三维渲染处理器中处理像素光栅化的方法和装置
公开(公告)号：US06791558B2
公开(公告)日：2004-09-14
申请号：US09920209
申请日：2001-08-01
申请人： Woo Chan Park , Tack Don Han , Il San Kim , Kil Whan Lee , Sung Bong Yang
发明人： Woo Chan Park , Tack Don Han , Il San Kim , Kil Whan Lee , Sung Bong Yang
IPC分类号： G09G536
CPC分类号： G06T15/40
摘要： A method and apparatus for processing pixel rasterization in a 3D rendering processor is disclosed. According to the method and apparatus, the primary depth checking is performed before the performing of the texture mapping, and thus the unnecessary performing of the texture mapping can be removed. Also, the consistency problem can be simply and easily solved using the flag memory, and by performing the depth reading and depth checking twice, the hit rate of the pixel cache memory is heightened. Thus, the method and apparatus is effective in cost, performance, and power consumption.
摘要翻译：公开了一种在3D渲染处理器中处理像素光栅化的方法和装置。根据该方法和装置，在执行纹理映射之前执行主深度检查，从而可以消除纹理映射的不必要的执行。此外，使用标志存储器可以简单且容易地解决一致性问题，并且通过执行深度读取和深度检查两次，提高了像素高速缓冲存储器的命中率。因此，该方法和装置在成本，性能和功耗方面是有效的。

2. 发明申请

US20080106551A1 Rendering apparatus, method and medium 有权
标题翻译：渲染装置，方法和介质
公开(公告)号：US20080106551A1
公开(公告)日：2008-05-08
申请号：US11889629
申请日：2007-08-15
申请人： Seok-yoon Jung , Sang-duk Kim , Il-san Kim , Jae-ho Nah , Woo-chan Park , Tack-don Han
发明人： Seok-yoon Jung , Sang-duk Kim , Il-san Kim , Jae-ho Nah , Woo-chan Park , Tack-don Han
IPC分类号： G06T1/20
CPC分类号： G06T11/40
摘要： A rendering method, medium and apparatus for sequentially performing one or more third raster operations to test whether a fragment can be displayed as a pixel after sequentially performing one or more second raster operations to test whether the fragment can be displayed as the pixel, so as to provide efficient power consumption and rapid completion of rendering.
摘要翻译：一种渲染方法，介质和装置，用于在顺序执行一个或多个第二光栅操作以测试片段是否可以显示为像素之后，顺序地执行一个或多个第三光栅操作以测试片段是否可以显示为像素，以便提供高效的功耗和快速完成渲染。

3. 发明授权

US08379050B2 Rendering apparatus, method and medium 有权
标题翻译：渲染装置，方法和介质
公开(公告)号：US08379050B2
公开(公告)日：2013-02-19
申请号：US11889629
申请日：2007-08-15
申请人： Seok-yoon Jung , Sang-duk Kim , Il-san Kim , Jae-ho Nah , Woo-chan Park , Tack-don Han
发明人： Seok-yoon Jung , Sang-duk Kim , Il-san Kim , Jae-ho Nah , Woo-chan Park , Tack-don Han
IPC分类号： G06T15/40 , G06T15/50 , G09G5/00
CPC分类号： G06T11/40
摘要： A rendering method, medium and apparatus for sequentially performing one or more third raster operations to test whether a fragment can be displayed as a pixel after sequentially performing one or more second raster operations to test whether the fragment can be displayed as the pixel, so as to provide efficient power consumption and rapid completion of rendering.
摘要翻译：一种渲染方法，介质和装置，用于在顺序执行一个或多个第二光栅操作以测试片段是否可以显示为像素之后，顺序地执行一个或多个第三光栅操作以测试片段是否可以显示为像素，以便提供高效的功耗和快速完成渲染。

4. 发明授权

US07042462B2 Pixel cache, 3D graphics accelerator using the same, and method therefor 有权
标题翻译：像素缓存，3D图形加速器使用相同，及其方法
公开(公告)号：US07042462B2
公开(公告)日：2006-05-09
申请号：US10731434
申请日：2003-12-10
申请人： Jae-hyun Kim , Yong-je Kim , Tack-don Han , Woo-chan Park , Gil-hwan Lee , Il-san Kim
发明人： Jae-hyun Kim , Yong-je Kim , Tack-don Han , Woo-chan Park , Gil-hwan Lee , Il-san Kim
IPC分类号： G09G5/36 , G06T15/40
CPC分类号： G06T15/005 , G06T15/405
摘要： An effective structure of a pixel cache for use in a three-dimensional (3D) graphics accelerator is provided. The pixel cache includes a z-data storage unit that reads z-data from a frame memory and provides the read z-data to a pixel rasterization pipeline; and a color data storage unit that in advance reads and stores color data from the frame memory at the same time when the z-data storage unit reads the z-data from the frame memory, and provides the color data to the pixel rasterization pipeline only when the result of predetermined z-test is determined to be a success in the pixel rasterization pipeline. Accordingly, the pixel cache structure enables only color data required to be read and stored in advance before processing of the color data, thereby preventing access latency, increasing the efficiency of a color cache, and reducing power consumption.
摘要翻译：提供了用于三维（3D）图形加速器的像素高速缓存的有效结构。像素高速缓存包括z数据存储单元，其从帧存储器读取z数据，并将读取的z数据提供给像素光栅化管线; 以及彩色数据存储单元，其在z数据存储单元从帧存储器读取z数据的同时，预先从帧存储器读取和存储颜色数据，并且仅将颜色数据提供给像素光栅化管线当预定的z检验的结果被确定为在像素光栅化管线中成功时。因此，在处理彩色数据之前，像素高速缓存结构仅能够预先读取和存储需要的颜色数据，从而防止访问等待时间，提高彩色高速缓存的效率，并降低功耗。

5. 发明授权

US07886097B2 Bus arbitration system, medium, and method 失效
标题翻译：总线仲裁系统，媒介和方法
公开(公告)号：US07886097B2
公开(公告)日：2011-02-08
申请号：US11812946
申请日：2007-06-22
申请人： Seok-yoon Jung , Il-san Kim , Jin-hong Park , Tack-don Han
发明人： Seok-yoon Jung , Il-san Kim , Jin-hong Park , Tack-don Han
IPC分类号： G06F13/40
CPC分类号： G06F13/364
摘要： A bus arbitration system, medium, and method. The bus arbitration system can arbitrate access to a bus for a plurality of masters, requesting the use of a bus to which at least one slave is connected, and may include a bus use granting unit that outputs a plurality of bus grant signals for granting the use of the bus to the plurality of masters that request the use of the bus at the same time, a simultaneous processing available signal selecting unit that selects a predetermined number of operation instruction signals having a predetermined similarity, from among a plurality of operation instruction signals that are input from the masters, in response to the bus grant signals, and an operation instructing unit that simultaneously transmits the selected operation instruction signals to the slave through the bus.
摘要翻译：总线仲裁系统，媒介和方法。总线仲裁系统可以仲裁访问多个主机的总线，请求使用至少一个从机连接到的总线，并且可以包括总线使用许可单元，其输出多个总线授权信号以授予使用总线到同时请求使用总线的多个主机，同时处理可用信号选择单元从多个操作指令信号中选择预定数量的具有预定相似度的操作指令信号以及响应于总线许可信号从主机输入的操作指令单元，以及通过总线同时将所选择的操作指令信号发送到从机的操作指令单元。

6. 发明申请

US20080005435A1 Bus arbitration system, medium, and method 失效
标题翻译：总线仲裁系统，媒介和方法
公开(公告)号：US20080005435A1
公开(公告)日：2008-01-03
申请号：US11812946
申请日：2007-06-22
申请人： Seok-yoon Jung , Il-san Kim , Jin-hong Park , Tack-don Han
发明人： Seok-yoon Jung , Il-san Kim , Jin-hong Park , Tack-don Han
IPC分类号： G06F13/00
CPC分类号： G06F13/364
摘要： A bus arbitration system, medium, and method. The bus arbitration system can arbitrate access to a bus for a plurality of masters, requesting the use of a bus to which at least one slave is connected, and may include a bus use granting unit that outputs a plurality of bus grant signals for granting the use of the bus to the plurality of masters that request the use of the bus at the same time, a simultaneous processing available signal selecting unit that selects a predetermined number of operation instruction signals having a predetermined similarity, from among a plurality of operation instruction signals that are input from the masters, in response to the bus grant signals, and an operation instructing unit that simultaneously transmits the selected operation instruction signals to the slave through the bus.
摘要翻译：总线仲裁系统，媒介和方法。总线仲裁系统可以仲裁访问多个主机的总线，请求使用至少一个从机连接到的总线，并且可以包括总线使用许可单元，其输出多个总线授权信号以授予使用总线到同时请求使用总线的多个主机，同时处理可用信号选择单元从多个操作指令信号中选择预定数量的具有预定相似度的操作指令信号以及响应于总线许可信号从主机输入的操作指令单元，以及通过总线同时将所选择的操作指令信号发送到从机的操作指令单元。

7. 发明申请

US20060098021A1 Graphics system and memory device for three-dimensional graphics acceleration and method for three dimensional graphics processing 审中-公开
标题翻译：用于三维图形加速的图形系统和存储器件以及三维图形处理方法
公开(公告)号：US20060098021A1
公开(公告)日：2006-05-11
申请号：US11268575
申请日：2005-11-08
申请人： Jung-Hwan Rim , Tack Han , Kyung-Ho Kim , Joo-Kwang Kim , Sung-Soo Byeon , Il-San Kim , Woo-Chan Park
发明人： Jung-Hwan Rim , Tack Han , Kyung-Ho Kim , Joo-Kwang Kim , Sung-Soo Byeon , Il-San Kim , Woo-Chan Park
IPC分类号： G06F12/02
CPC分类号： G06T15/005 , G06F12/0223 , G06T1/20
摘要： A graphics system and a memory device for three-dimensional (3D) graphics acceleration, and a method for 3D graphics processing, are provided. In a memory device in a graphics system for 3D graphics processing, a memory structure includes a first memory area allocated to a texture buffer for storing texture data, and a second memory area allocated to a frame buffer for storing frame data in pixels. A comparator controls the memory structure to operate as the texture buffer if an input address to the memory structure indicates the first memory area and controls the memory structure to operate as the frame buffer if the input address indicates the second memory area. If the memory structure operates as the frame buffer, an ALU performs depth comparison or alpha-blending on input frame data and frame data read from the frame buffer.
摘要翻译：提供了用于三维（3D）图形加速的图形系统和存储器件，以及用于3D图形处理的方法。在用于3D图形处理的图形系统中的存储器件中，存储器结构包括分配给用于存储纹理数据的纹理缓冲器的第一存储器区域和分配给用于以像素存储帧数据的帧缓冲器的第二存储器区域。如果存储器结构的输入地址指示第一存储器区域并且如果输入地址指示第二存储区域则控制存储器结构作为帧缓冲器操作，则比较器控制存储器结构作为纹理缓冲器操作。如果存储器结构作为帧缓冲器操作，则ALU对从帧缓冲器读取的输入帧数据和帧数据执行深度比较或α混合。

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