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1. 发明授权

US09339018B2 Selective infarcted-tissue-targeting bacteria and use thereof 有权
标题翻译：选择性梗死组织靶向细菌及其用途
公开(公告)号：US09339018B2
公开(公告)日：2016-05-17
申请号：US13322637
申请日：2010-05-27
申请人： Hyon El Choy , Jung-Joon Min , Hyung Seok Kim , Yeongjin Hong
发明人： Hyon El Choy , Jung-Joon Min , Hyung Seok Kim , Yeongjin Hong
IPC分类号： A61K48/00 , A61K35/74 , A61K49/00 , A01K67/027 , C07K14/255 , A61K35/00
CPC分类号： A01K67/027 , A01K2207/12 , A01K2227/105 , A01K2267/0375 , A61K48/0033 , A61K2035/11 , C07K14/255 , C12N2830/001
摘要： The present invention relates to bacteria which specifically target infarcted tissue and use thereof. The present invention provides a selective infarcted tissue-targeting bacterium for the first time, and can be used in selectively delivering drugs to the infarcted tissue or in selectively imaging the infarcted tissue. The infarcted tissue-targeting bacterium of the present invention can finish treatments by using antibiotics, and therefore, have remarkable advantages as compared to gene therapy using recombinant viruses. The infarcted tissue-targeting bacterium of the present invention have a significantly high affinity and specificity to infarcted myocardium or infarcted brain, thereby significantly reducing undesired transfections in the organs or tissues other than the heart. The gene expression by the infarcted tissue-targeting bacterium of the present invention in infarcted myocardium or infarcted brain is remotely controllable.
摘要翻译：本发明涉及特异性靶向梗死组织的细菌及其应用。本发明首次提供了选择性梗塞的组织靶向细菌，并且可以用于选择性地将药物递送至梗死组织或选择性地成像梗塞组织。本发明的梗塞组织靶向细菌可以通过使用抗生素来完成治疗，因此与使用重组病毒的基因治疗相比具有显着的优点。本发明的梗死组织靶向细菌对梗塞的心肌或梗死的脑具有显着高的亲和性和特异性，从而显着减少心脏以外的器官或组织中不期望的转染。本发明的梗死组织靶向细菌在梗死心肌或梗死的脑中的基因表达是可远程控制的。

2. 发明授权

US08941520B2 Resistor-based Σ-ΔDAC 有权
标题翻译：基于电阻和电阻的DAC
公开(公告)号：US08941520B2
公开(公告)日：2015-01-27
申请号：US13995156
申请日：2011-09-30
申请人： Hyung Seok Kim , Yee W. Li , Ashoke Ravi , Hasnain Lakdawala
发明人： Hyung Seok Kim , Yee W. Li , Ashoke Ravi , Hasnain Lakdawala
IPC分类号： H03M3/00 , H03M1/08 , H03M1/80 , H03M1/78 , H03M1/74 , H03M1/00 , H03M1/12 , G09G3/36
CPC分类号： H03M3/50 , G09G3/3688 , H03M1/00 , H03M1/0863 , H03M1/12 , H03M1/747 , H03M1/785 , H03M1/808 , H03M3/30 , H03M3/502
摘要： An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor is coupled to an output node of the resistor-ladder network. An output voltage is generated at the output node that is based on the multi-bit input signal. In one exemplary embodiment, the multi-bit input signal is a sigma-delta (ΣΔ) modulated multi-bit input signal. In another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are related by a binary weighting. In still another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are substantially equal.
摘要翻译：逆变器驱动的电阻梯形数模（DAC）转换器包括一个电阻梯形网络，包括一个多位输入信号的每个位信号的电阻。电阻梯形网络的每个电阻器包括输入端和输出端。每个电阻器的输入端耦合到多位输入信号的对应位信号，并且每个电阻器的输出端耦合到电阻梯形网络的输出节点。在输出节点处产生基于多位输入信号的输出电压。在一个示例性实施例中，多比特输入信号是Σ-Δ（＆Sgr＆amp; Dgr）调制的多位输入信号。在另一示例性实施例中，电阻梯形网络的电阻器的电阻值通过二进制加权相关。在又一示例性实施例中，电阻梯形网络的电阻器的电阻值基本相等。

3. 发明授权

US08929148B2 Semiconductor memory device having improved erase characteristic of memory cells and erase method thereof 有权
标题翻译：具有改善的存储单元的擦除特性的半导体存储器件及其擦除方法
公开(公告)号：US08929148B2
公开(公告)日：2015-01-06
申请号：US13293391
申请日：2011-11-10
申请人： Hyung Seok Kim
发明人： Hyung Seok Kim
IPC分类号： G11C11/36
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/3409 , G11C16/3445
摘要： A semiconductor memory device includes a plurality of memory blocks configured to include memory cells, a voltage supply circuit configured to supply an erase voltage for an erase operation of a memory block selected from the memory blocks and supply an erase verify voltage and an erase pass voltage for an erase verify operation of the memory block selected from the memory blocks, and a control logic configured to group word lines per specific word lines, when the erase verify operation for the selected memory block is performed, and control the voltage supply circuit so that one or more of the erase verify voltage and the erase pass voltage rise whenever the erase verify operation is performed.
摘要翻译：一种半导体存储器件包括：多个存储块，被配置为包括存储单元;电压供给电路，被配置为提供擦除电压，用于从存储块中选择的存储块的擦除操作，并提供擦除验证电压和擦除通过电压用于从存储块中选择的存储块的擦除验证操作;以及控制逻辑，被配置为当执行所选择的存储块的擦除验证操作时，每个特定字线对字线进行分组，并且控制电压供应电路，使得只要执行擦除验证操作，擦除验证电压和擦除通过电压中的一个或多个上升。

4. 发明申请

US20120100661A1 INK FOR FORMING THIN FILM OF SOLAR CELLS AND METHOD FOR PREPARING THE SAME, CIGS THIN FILM SOLAR CELL USING THE SAME AND MANUFACTURING METHOD THEREOF 失效
标题翻译：用于形成太阳能电池薄膜的墨水及其制备方法，CIGS薄膜太阳能电池及其制造方法
公开(公告)号：US20120100661A1
公开(公告)日：2012-04-26
申请号：US13338136
申请日：2011-12-27
申请人： Young-Ho Choe , Young-Hee Lee , Yong-Woo Choi , Hyung-Seok Kim , Ho-Gyoung Kim
发明人： Young-Ho Choe , Young-Hee Lee , Yong-Woo Choi , Hyung-Seok Kim , Ho-Gyoung Kim
IPC分类号： H01L31/18 , B82Y40/00
CPC分类号： H01L21/02628 , C09D11/037 , C09D11/52 , H01L21/02422 , H01L21/02491 , H01L21/02568 , H01L21/02601 , H01L31/0322 , Y02E10/541 , Y02P70/521
摘要： Discussed are an ink containing nanoparticles for formation of thin film of a solar cell and its preparation method, CIGS thin film solar cell having at least one light absorption layer formed by coating or printing the above ink containing nanoparticles on a rear electrode, and a process for manufacturing the same. More particularly, the above absorption layer includes Cu, In, Ga and Se elements as constitutional ingredients thereof and such elements exist in the light absorption layer by coating or printing an ink that contains Cu2Se nanoparticles and (In,Ga)2Se3 nanoparticles on the rear electrode, and heating the treated electrode with the ink. Since Cu(In,Ga)Se2 (CIGS) thin film is formed using the ink containing nanoparticles, a simple process is used without requirement of vacuum processing or complex equipment and particle size of the thin film, Ga doping concentration, etc., can be easily regulated.
摘要翻译：讨论了含有形成太阳能电池薄膜的纳米颗粒的油墨及其制备方法，CIGS薄膜太阳能电池具有通过在后电极上涂布或印刷上述含有墨的纳米颗粒而形成的至少一个光吸收层，以及工艺制造相同。更具体地，上述吸收层包括Cu，In，Ga和Se元素作为其构成成分，并且这些元素通过涂覆或印刷包含Cu 2 Se纳米颗粒和（In，Ga）2 Si 3纳米颗粒在后面的油墨而存在于光吸收层中电极，并用油墨加热处理过的电极。由于使用含有纳米颗粒的油墨形成Cu（In，Ga）Se 2（CIGS）薄膜，所以使用简单的工艺不需要真空处理或复杂的设备和薄膜的粒径，Ga掺杂浓度等容易调节。

5. 发明授权

US07598137B2 Method for manufacturing semiconductor device including MIM capacitor 失效
标题翻译：包括MIM电容器的半导体器件的制造方法
公开(公告)号：US07598137B2
公开(公告)日：2009-10-06
申请号：US11319492
申请日：2005-12-29
申请人： Hyung Seok Kim
发明人： Hyung Seok Kim
IPC分类号： H01L21/8242
CPC分类号： H01L28/40 , Y10S438/957
摘要： A semiconductor device including a metal-insulator-metal (MIM) capacitor is manufactured such that a via for connecting upper and lower conductive layers is formed through an insulating interlayer after a silicon nitride layer is deposited as a thick layer on the insulating interlayer. This protects an edge of a MIM structure during an etching process that forms the via. In addition, a fluorine gas can be used in a gas stripping process to remove a polymer residue when stripping the photoresist used to form the via. The MIM capacitor has an insulator layer. The method of manufacturing the device includes forming an insulator layer of the MIM capacitor to a predetermined thickness on the insulating interlayer. The predetermined thickness is equal to the desired thickness plus an augmentation thickness, and the augmentation thickness is determined according to the stripping process for removing the photoresist pattern.
摘要翻译：制造包括金属 - 绝缘体 - 金属（MIM）电容器的半导体器件，使得在绝缘中间层上沉积氮化硅层作为厚层之后，通过绝缘中间层形成用于连接上导电层和下导电层的通孔。这在保护形成通孔的蚀刻工艺期间保护MIM结构的边缘。此外，当汽提用于形成通孔的光致抗蚀剂时，氟气可用于气体剥离工艺以除去聚合物残余物。 MIM电容器具有绝缘体层。制造该器件的方法包括在绝缘中间层上形成MIM电容器的绝缘体层至预定的厚度。预定厚度等于期望的厚度加上增加厚度，并且根据用于去除光致抗蚀剂图案的剥离过程确定增加厚度。

6. 发明授权

US07301519B2 STN LCD driver using circuit with fewer capacitors and method therefor 有权
标题翻译： STN LCD驱动器使用电路较少的电容器及其方法
公开(公告)号：US07301519B2
公开(公告)日：2007-11-27
申请号：US10649557
申请日：2003-08-26
申请人： Hyung-seok Kim
发明人： Hyung-seok Kim
IPC分类号： G09G3/36
CPC分类号： G09G3/3696 , G09G3/3614 , G09G3/3622
摘要： An STN LCD driver using a circuit with a reduced number of capacitors for driving voltage stabilization, and a method therefor, are provided. The STN LCD driver includes a driving voltage generating circuit, a common/segment driving circuit, first through third capacitors, and a control circuit. The driving voltage generating circuit generates first through fifth driving voltages to output the generated driving voltages via first through fifth output terminals. The common/segment driving circuit, which is controlled by a driving polarity signal, receives the first through fifth driving voltages and generates a common driving signal and a segment driving signal. The first capacitor is connected between the first output terminal and a ground voltage. The control circuit controls connection of the output terminals and the capacitors in response to the driving polarity signal, in order to reduce the number of the capacitors for driving voltage stabilization.
摘要翻译：提供了使用具有减少数量的用于驱动电压稳定化的电容器的电路的STN LCD驱动器及其方法。 STN LCD驱动器包括驱动电压产生电路，公共/分段驱动电路，第一至第三电容器和控制电路。驱动电压产生电路产生第一至第五驱动电压，以经由第一至第五输出端输出产生的驱动电压。由驱动极性信号控制的公共/段驱动电路接收第一至第五驱动电压，并产生公共驱动信号和段驱动信号。第一电容器连接在第一输出端子和接地电压之间。控制电路响应于驱动极性信号控制输出端子和电容器的连接，以便减少用于驱动电压稳定的电容器的数量。

7. 发明授权

US08976583B2 Non-volatile semiconductor memory device and reading method thereof 有权
标题翻译：非易失性半导体存储器件及其读取方法
公开(公告)号：US08976583B2
公开(公告)日：2015-03-10
申请号：US13605779
申请日：2012-09-06
申请人： Hyung-Seok Kim
发明人： Hyung-Seok Kim
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0483 , G11C16/06 , G11C16/3427
摘要： Provided are a semiconductor memory device has improved read disturbance characteristics as well as improved retention characteristics at a high temperature, and a reading method thereof. The non-volatile semiconductor memory device includes at least one bit line; and a cell string configured to be coupled with the bit line respectively, and include normal memory cells and dummy memory cells that are alternately coupled with each other, where normal data are programmed and read to and from the normal memory cells, and dummy memory cells are programmed with dummy data.
摘要翻译：提供了一种具有改善的读取干扰特性以及在高温下改进的保持特性的半导体存储器件及其读取方法。非易失性半导体存储器件包括至少一个位线; 以及配置为分别与位线耦合的单元串，并且包括彼此交替耦合的正常存储器单元和虚拟存储单元，其中正常数据被编程并从正常存储单元读取，并且存储单元用伪数据编程。

8. 发明申请

US20130271305A1 RESISTOR-BASED SIGMA-DELTA DAC 有权
标题翻译：基于电阻的SIGMA-DELTA DAC
公开(公告)号：US20130271305A1
公开(公告)日：2013-10-17
申请号：US13995156
申请日：2011-09-30
申请人： Hyung Seok Kim , Yee W. Li , Ashoke Ravi , Hasnain Lakdawala
发明人： Hyung Seok Kim , Yee W. Li , Ashoke Ravi , Hasnain Lakdawala
IPC分类号： H03M3/00 , H03M1/78
CPC分类号： H03M3/50 , G09G3/3688 , H03M1/00 , H03M1/0863 , H03M1/12 , H03M1/747 , H03M1/785 , H03M1/808 , H03M3/30 , H03M3/502
摘要： An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor is coupled to an output node of the resistor-ladder network. An output voltage is generated at the output node that is based on the multi-bit input signal. In one exemplary embodiment, the multi-bit input signal is a sigma-delta (ΣΔ) modulated multi-bit input signal. In another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are related by a binary weighting. In still another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are substantially equal.
摘要翻译：逆变器驱动的电阻梯形数模（DAC）转换器包括一个电阻梯形网络，包括一个多位输入信号的每个位信号的电阻。电阻梯形网络的每个电阻器包括输入端和输出端。每个电阻器的输入端耦合到多位输入信号的对应位信号，并且每个电阻器的输出端耦合到电阻梯形网络的输出节点。在输出节点处产生基于多位输入信号的输出电压。在一个示例性实施例中，多位输入信号是Σ-Δ（SigmaDelta）调制的多位输入信号。在另一示例性实施例中，电阻梯形网络的电阻器的电阻值通过二进制加权相关。在又一示例性实施例中，电阻梯形网络的电阻器的电阻值基本相等。

9. 发明授权

US08526239B2 Semiconductor memory device and method of operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US08526239B2
公开(公告)日：2013-09-03
申请号：US13096870
申请日：2011-04-28
申请人： Hyung Seok Kim
发明人： Hyung Seok Kim
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/26 , G11C16/344
摘要： A semiconductor memory device includes a memory string coupled to a bit line, a page buffer configured to sense a sensing current of the bit line in an erase verification operation or a program verification operation, and a sensing control circuit configured to differently set a level of the sensing current in the erase verification operation and the program verification operation in order to sense the threshold voltage level of a selected memory cell of the memory string.
摘要翻译：半导体存储器件包括耦合到位线的存储器串，配置为在擦除验证操作或程序验证操作中感测位线的感测电流的页缓冲器，以及感测控制电路，其被配置为不同地设置擦除验证操作中的感测电流和程序验证操作，以便感测存储器串的选定存储单元的阈值电压电平。

10. 发明申请

US20130163334A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20130163334A1
公开(公告)日：2013-06-27
申请号：US13601578
申请日：2012-08-31
申请人： Hyung Seok KIM
发明人： Hyung Seok KIM
IPC分类号： G11C16/12 , G11C16/34 , G11C16/04
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/3418
摘要： A semiconductor memory device and a method of operating the same include a circuit group configured to apply a program maintaining voltage between the program prohibition voltage and the program permission voltage to bit lines connected to programmed memory cells to prevent a decrease in threshold voltage.
摘要翻译：半导体存储器件及其操作方法包括：电路组，被配置为将程序禁止电压和程序允许电压之间的程序保持在连接到编程的存储器单元的位线上，以防止阈值电压的降低。

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