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1. 发明授权

US08796844B2 Package structure 有权
标题翻译：包装结构
公开(公告)号：US08796844B2
公开(公告)日：2014-08-05
申请号：US13393746
申请日：2009-09-02
申请人： Hwee-Seng Jimmy Chew , Chee Kian Ong
发明人： Hwee-Seng Jimmy Chew , Chee Kian Ong
IPC分类号： H01L23/02 , H01L23/34 , H05K1/02 , H01L25/065 , H01L23/538
CPC分类号： H01L25/0655 , H01L23/5386 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/00014 , H01L2924/09701 , H01L2924/15311 , H05K1/0243 , H05K2201/10378 , H05K2201/10522 , H05K2201/10674 , H01L2224/0401
摘要： A package structure including a first semiconductor element, a second semiconductor element, a semiconductor interposer and a substrate is provided. The first semiconductor element includes multiple first conductive bumps. The second semiconductor element includes multiple second conductive bumps. The semiconductor interposer includes a connection motherboard, at least one signal wire and at least one signal conductive column. The signal wire is disposed on the connection motherboard. The two ends of the signal wire are electrically connected to one of the first conductive bumps and one of the second conductive bumps respectively. The signal conductive column is electrically connected to the signal wire. The substrate is electrically connected to the signal conductive column. The first and the second semiconductor elements have the same circuit structure. The substrate of the package structure can simultaneously form a signal communication path with the first and the second semiconductor element respectively.
摘要翻译：提供包括第一半导体元件，第二半导体元件，半导体插入器和基板的封装结构。第一半导体元件包括多个第一导电凸块。第二半导体元件包括多个第二导电凸块。半导体插入器包括连接母板，至少一个信号线和至少一个信号导电柱。信号线设置在连接母板上。信号线的两端分别电连接到第一导电凸块中的一个和第二导电凸块中的一个。信号导电柱与信号线电连接。衬底电连接到信号导电柱。第一和第二半导体元件具有相同的电路结构。封装结构的衬底可以分别同时形成与第一和第二半导体元件的信号通信路径。

2. 发明申请

US20080150107A1 FLIP CHIP IN PACKAGE USING FLEXIBLE AND REMOVABLE LEADFRAME 审中-公开
标题翻译：使用灵活和可拆卸的铅笔在包装中使用FLIP芯片
公开(公告)号：US20080150107A1
公开(公告)日：2008-06-26
申请号：US12043143
申请日：2008-03-06
申请人： Teck Tiong TAN , Hwee Seng Jimmy CHEW , Kok Yeow Eddy LIM , Abd. Razak Bin CHICHIK , Kee Kwang LAU , Chuan Wei WONG
发明人： Teck Tiong TAN , Hwee Seng Jimmy CHEW , Kok Yeow Eddy LIM , Abd. Razak Bin CHICHIK , Kee Kwang LAU , Chuan Wei WONG
IPC分类号： H01L23/495
CPC分类号： H01L23/3107 , H01L21/4821 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/49541 , H01L23/49548 , H01L24/16 , H01L24/97 , H01L2221/68345 , H01L2224/16 , H01L2224/16245 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/18301 , H01L2224/81
摘要： A method for forming semiconductor packages is disclosed. The method involves providing a support substrate and forming at least one conductive layer thereon. The method also includes coupling the at least one conductive layer to a support face of a film substrate for securing the at least one conductive layer to the support face and removing the support substrate from the at least one conductive layer. The at least one interconnector is adhered to the film substrate for forming an interposer. The method further involves bonding a integrated circuit chip to the at least one conductive layer of the interposer and disposing a compound over the support face to thereby encapsulate the integrated circuit chip and the least one conductive layer for forming an encapsulated package therefrom. Portions of the at least one conductive layer is then exposed by removing the film substrate from the encapsulated package.
摘要翻译：公开了一种用于形成半导体封装件的方法。该方法包括提供支撑衬底并在其上形成至少一个导电层。该方法还包括将至少一个导电层耦合到薄膜基底的支撑面，用于将至少一个导电层固定到支撑面上，并从至少一个导电层移除支撑基底。至少一个互连器粘附到膜基底上以形成插入件。该方法还包括将集成电路芯片接合到插入器的至少一个导电层并且在支撑面上方布置化合物，从而封装集成电路芯片和用于形成封装封装的至少一个导电层。然后通过从封装的包装中去除膜基材来暴露至少一个导电层的部分。

3. 发明申请

US20120153466A1 PACKAGE STRUCTURE 有权
标题翻译：包装结构
公开(公告)号：US20120153466A1
公开(公告)日：2012-06-21
申请号：US13393746
申请日：2009-09-02
申请人： Hwee-Seng Jimmy Chew , Chee Kian Ong
发明人： Hwee-Seng Jimmy Chew , Chee Kian Ong
IPC分类号： H01L23/498
CPC分类号： H01L25/0655 , H01L23/5386 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/00014 , H01L2924/09701 , H01L2924/15311 , H05K1/0243 , H05K2201/10378 , H05K2201/10522 , H05K2201/10674 , H01L2224/0401
摘要： A package structure including a first semiconductor element, a second semiconductor element, a semiconductor interposer and a substrate is provided. The first semiconductor element includes multiple first conductive bumps. The second semiconductor element includes multiple second conductive bumps. The semiconductor interposer includes a connection motherboard, at least one signal wire and at least one signal conductive column. The signal wire is disposed on the connection motherboard. The two ends of the signal wire are electrically connected to one of the first conductive bumps and one of the second conductive bumps respectively. The signal conductive column is electrically connected to the signal wire. The substrate is electrically connected to the signal conductive column. The first and the second semiconductor elements have the same circuit structure. The substrate of the package structure can simultaneously form a signal communication path with the first and the second semiconductor element respectively.
摘要翻译：提供包括第一半导体元件，第二半导体元件，半导体插入器和基板的封装结构。第一半导体元件包括多个第一导电凸块。第二半导体元件包括多个第二导电凸块。半导体插入器包括连接母板，至少一个信号线和至少一个信号导电柱。信号线设置在连接母板上。信号线的两端分别电连接到第一导电凸块中的一个和第二导电凸块中的一个。信号导电柱与信号线电连接。衬底电连接到信号导电柱。第一和第二半导体元件具有相同的电路结构。封装结构的衬底可以分别同时形成与第一和第二半导体元件的信号通信路径。

4. 发明申请

US20080088013A1 Chip and manufacturing method thereof 有权
标题翻译：芯片及其制造方法
公开(公告)号：US20080088013A1
公开(公告)日：2008-04-17
申请号：US11905482
申请日：2007-10-01
申请人： Hwee-Seng Jimmy Chew , Chee Kian Ong
发明人： Hwee-Seng Jimmy Chew , Chee Kian Ong
IPC分类号： H01L23/48
CPC分类号： H01L24/14 , H01L23/4827 , H01L23/50 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/17 , H01L2224/0345 , H01L2224/03912 , H01L2224/0401 , H01L2224/05082 , H01L2224/05083 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05184 , H01L2224/05552 , H01L2224/05553 , H01L2224/0558 , H01L2224/05644 , H01L2224/06153 , H01L2224/114 , H01L2224/11462 , H01L2224/1147 , H01L2224/116 , H01L2224/13012 , H01L2224/13016 , H01L2224/13023 , H01L2224/13027 , H01L2224/1308 , H01L2224/13082 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/141 , H01L2224/16227 , H01L2924/00013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/2064 , H01L2924/384 , H01L2924/00014 , H01L2924/01083 , H01L2224/13099 , H01L2924/00012
摘要： A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature.
摘要翻译：提供了一种半导体器件及其制造方法。半导体器件具有活性表面。半导体器件至少包括连接元件和至少一个凸块。连接元件设置在激活表面上并且具有小于100微米的最小尺寸。凸块设置在连接元件上，并且通过连接元件电连接到有源表面。凸块包括设置在连接元件上的柱部和设置在柱部的顶部的顶部。柱部分具有平行于活动表面的第一尺寸和第二尺寸。第一维度长于第二维的1.2倍。顶部由焊料组成，并在确定的温度下熔化。支柱部分不会在确定的温度下熔化。

5. 发明申请

US20070284420A1 INTEGRATED CIRCUIT CHIP FORMED ON SUBSTRATE 审中-公开
标题翻译：基板上集成电路芯片
公开(公告)号：US20070284420A1
公开(公告)日：2007-12-13
申请号：US11423725
申请日：2006-06-13
申请人： Teck Tiong Tan , Hwee Seng Jimmy Chew
发明人： Teck Tiong Tan , Hwee Seng Jimmy Chew
IPC分类号： B23K31/02
CPC分类号： B23K1/0016 , H01L24/12 , H01L24/16 , H01L24/81 , H01L2224/05568 , H01L2224/05573 , H01L2224/05624 , H01L2224/13023 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/16237 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2224/8121 , H01L2224/81815 , H01L2224/83102 , H01L2224/92125 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H05K3/3436 , H05K2201/0367 , Y02P70/613 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2224/29099
摘要： A method for coupling a semiconductor substrate to a receiving substrate is disclosed. The method comprising the step of providing a receiving substrate having at least one receiving pad formed thereon, the at least one receiving pad having a face and a portion substantially extending from the periphery of the face to the receiving substrate. The method also involves the step of providing a semiconductor substrate having at least one bonding pad formed thereon and at least one pillar extending from the at least one bonding pad towards the at least one receiving pad, the at least one pillar having a reflowable and a non-reflowable portion. The method further involves the step of positioning the semiconductor substrate over the receiving substrate for facing the at least one receiving pad towards the at least one pillar, and reflowing the reflowable portion substantially over the face and substantially onto the portion.
摘要翻译：公开了一种将半导体衬底耦合到接收衬底的方法。该方法包括提供具有形成在其上的至少一个接收垫的接收衬底的步骤，所述至少一个接收衬垫具有面和基本上从面的周边延伸到接收衬底的部分。该方法还包括提供具有形成在其上的至少一个焊盘和至少一个从至少一个焊盘朝向至少一个接收焊盘的支柱的半导体衬底的步骤，该至少一个支柱具有可回流和不可回流部分。该方法还包括将半导体衬底定位在接收衬底上用于面向至少一个接收衬垫朝向至少一个支柱的步骤，并且将可回流部分基本上回流到面部上并且基本上在该部分上。

6. 发明授权

US08846519B2 Interconnections for fine pitch semiconductor devices and manufacturing method thereof 有权
标题翻译：细间距半导体器件的互连及其制造方法
公开(公告)号：US08846519B2
公开(公告)日：2014-09-30
申请号：US13467635
申请日：2012-05-09
申请人： Hwee-Seng Jimmy Chew , Chee Kian Ong
发明人： Hwee-Seng Jimmy Chew , Chee Kian Ong
IPC分类号： H01L21/44
CPC分类号： H01L24/14 , H01L23/4827 , H01L23/50 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/17 , H01L2224/0345 , H01L2224/03912 , H01L2224/0401 , H01L2224/05082 , H01L2224/05083 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05184 , H01L2224/05552 , H01L2224/05553 , H01L2224/0558 , H01L2224/05644 , H01L2224/06153 , H01L2224/114 , H01L2224/11462 , H01L2224/1147 , H01L2224/116 , H01L2224/13012 , H01L2224/13016 , H01L2224/13023 , H01L2224/13027 , H01L2224/1308 , H01L2224/13082 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/141 , H01L2224/16227 , H01L2924/00013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/2064 , H01L2924/384 , H01L2924/00014 , H01L2924/01083 , H01L2224/13099 , H01L2924/00012
摘要： A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed on the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is more than 1.2 times the second dimension. The top part is composed of solder and will melt under a pre-determined temperature. The pillar part will not melt under the pre-determined temperature.
摘要翻译：提供了一种半导体器件及其制造方法。半导体器件具有活性表面。半导体器件至少包括连接元件和至少一个凸块。连接元件设置在激活表面上并且具有小于100微米的最小尺寸。凸块设置在连接元件上，并且通过连接元件电连接到有源表面。凸块包括设置在连接元件上的柱部和设置在柱部的顶部上的顶部。柱部分具有平行于活动表面的第一尺寸和第二尺寸。第一维是第二维的1.2倍以上。顶部由焊料组成，并在预定温度下熔化。支柱部分在预定温度下不会熔化。

7. 发明申请

US20110267789A1 ETCH-BACK TYPE SEMICONDUCTOR PACKAGE, SUBSTRATE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：背面型半导体封装，基板及其制造方法
公开(公告)号：US20110267789A1
公开(公告)日：2011-11-03
申请号：US13097033
申请日：2011-04-28
申请人： Hwee-Seng Jimmy CHEW , Shoa-Siong Lim , Kian-Hock Lim
发明人： Hwee-Seng Jimmy CHEW , Shoa-Siong Lim , Kian-Hock Lim
IPC分类号： H05K1/18 , H05K1/09 , H05K1/11 , H01L21/56 , B05D5/12 , B05D1/36
CPC分类号： H01L23/49503 , H01L21/4821 , H01L21/4832 , H01L21/56 , H01L21/561 , H01L21/6835 , H01L23/3107 , H01L23/49548 , H01L23/49582 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/83 , H01L24/85 , H01L24/97 , H01L2224/27013 , H01L2224/2919 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48253 , H01L2224/48611 , H01L2224/48639 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48664 , H01L2224/73265 , H01L2224/83051 , H01L2224/83101 , H01L2224/83855 , H01L2224/85001 , H01L2224/85411 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/85464 , H01L2224/92 , H01L2224/92247 , H01L2224/97 , H01L2924/01006 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/10253 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package, a substrate and a manufacturing method thereof are provided. The substrate comprises a conductive carrier, a first metal layer and a second metal layer. The first metal layer is formed on the conductive carrier and comprises an lead pad having an upper surface. The second metal layer is formed on the first metal layer and comprises a bond pad. The bond pad overlaps and is in contact with the upper surface of the first metal layer. The upper surface of the lead pad is partially exposed. A part of the bond pad overhang outward from the edge of the lead pad.
摘要翻译：提供半导体封装，基板及其制造方法。衬底包括导电载体，第一金属层和第二金属层。第一金属层形成在导电载体上，并且包括具有上表面的引线焊盘。第二金属层形成在第一金属层上并且包括接合焊盘。接合焊盘重叠并与第一金属层的上表面接触。引线板的上表面部分露出。接合焊盘的一部分从引线焊盘的边缘向外突出。

8. 发明授权

US09396982B2 Semiconductor device carrier for fine pitch packaging miniaturization and manufacturing method thereof 有权
标题翻译：用于精细间距包装的半导体器件载体小型化及其制造方法
公开(公告)号：US09396982B2
公开(公告)日：2016-07-19
申请号：US12292813
申请日：2008-11-26
申请人： Hwee-Seng Jimmy Chew , Chee Kian Ong , Bin Chichik Abd. Razak
发明人： Hwee-Seng Jimmy Chew , Chee Kian Ong , Bin Chichik Abd. Razak
IPC分类号： H01L23/48 , H01L21/683 , H01L23/498 , H01L23/00
CPC分类号： H01L25/0657 , H01L21/4839 , H01L21/4853 , H01L21/486 , H01L21/563 , H01L21/6835 , H01L23/49558 , H01L23/49575 , H01L23/49816 , H01L23/49861 , H01L24/13 , H01L24/16 , H01L2221/68345 , H01L2224/0554 , H01L2224/05573 , H01L2224/131 , H01L2224/16 , H01L2224/16057 , H01L2224/16245 , H01L2225/06517 , H01L2225/0652 , H01L2924/00013 , H01L2924/00014 , H01L2924/01068 , H01L2924/01079 , H01L2924/014 , H01L2224/13099 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.
摘要翻译：提供半导体封装及其制造方法。封装元件具有第一绝缘层，并且多个孔设置在第一绝缘层的第一表面上。此外，多个封装迹线嵌入在绝缘层中并连接到孔的另一端。这些孔用作将焊球连接到封装迹线的定位设置，使得半导体芯片的信号通过芯片的导体连接到封装迹线，并且还通过焊球外部传输。第一绝缘层的材料的弹性模量优选大于1.0GPa。

9. 发明授权

US09287157B2 Semiconductor element for package miniaturization 有权
标题翻译：半导体元件封装小型化
公开(公告)号：US09287157B2
公开(公告)日：2016-03-15
申请号：US12826307
申请日：2010-06-29
申请人： Hwee-Seng Jimmy Chew , Chee Kian Ong , Bin Chichik Abd. Razak
发明人： Hwee-Seng Jimmy Chew , Chee Kian Ong , Bin Chichik Abd. Razak
IPC分类号： H01L23/495 , H01L21/683 , H01L23/498 , H01L23/00
CPC分类号： H01L25/0657 , H01L21/4839 , H01L21/4853 , H01L21/486 , H01L21/563 , H01L21/6835 , H01L23/49558 , H01L23/49575 , H01L23/49816 , H01L23/49861 , H01L24/13 , H01L24/16 , H01L2221/68345 , H01L2224/0554 , H01L2224/05573 , H01L2224/131 , H01L2224/16 , H01L2224/16057 , H01L2224/16245 , H01L2225/06517 , H01L2225/0652 , H01L2924/00013 , H01L2924/00014 , H01L2924/01068 , H01L2924/01079 , H01L2924/014 , H01L2224/13099 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor element that includes a forsy patterned conductive layer, a second pattern conductive layer and an insulating layer. The first surface of the second patterned conductive layer is connected to a second surface of the first patterned conductive layer. The insulating layer includes at least one space on a second surface thereof. The first patterned conductive layer and the second patterned conductive layer are embedded in the insulating layer between a first surface and a second surface thereof, the first surface of the first patterned conductive layer is entirely exposed on a first surface of the insulating layer, a second surface of the second patterned conductive layer is entirely exposed on the second surface of the insulating layer, and the space exposes the second surface of the first patterned conductive layer.
摘要翻译：一种半导体元件，包括伪造的图案化导电层，第二图案导电层和绝缘层。第二图案化导电层的第一表面连接到第一图案化导电层的第二表面。绝缘层在其第二表面上包括至少一个空间。将第一图案化导电层和第二图案化导电层嵌入在第一表面和第二表面之间的绝缘层中，第一图案化导电层的第一表面完全暴露在绝缘层的第一表面上，第二图案导电层第二图案化导电层的表面完全暴露在绝缘层的第二表面上，并且空间暴露第一图案化导电层的第二表面。

10. 发明授权

US08709874B2 Manufacturing method for semiconductor device carrier and semiconductor package using the same 有权
标题翻译：半导体器件载体和使用其的半导体封装的制造方法
公开(公告)号：US08709874B2
公开(公告)日：2014-04-29
申请号：US13222792
申请日：2011-08-31
申请人： Hwee-Seng Jimmy Chew , Kian-Hock Lim , Oviso Dominador Jr Fortaleza , Shoa-Siong Raymond Lim
发明人： Hwee-Seng Jimmy Chew , Kian-Hock Lim , Oviso Dominador Jr Fortaleza , Shoa-Siong Raymond Lim
IPC分类号： H01L21/56
CPC分类号： H01L23/562 , H01L23/293 , H01L23/3114 , H01L23/3121 , H01L23/49513 , H01L23/4952 , H01L23/49524 , H01L23/49541 , H01L23/49582 , H01L23/49861 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/32227 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/12042 , H01L2924/15787 , H01L2924/181 , Y10T29/49155 , H01L2224/85 , H01L2224/81 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A conductive carrier having a first surface and a second surface is provided. The conductive trace layer is formed on the second surface of the conductive carrier. A conductive stud layer is formed on the conductive trace layer. A dielectric layer is formed on the conductive layer to encapsulate the conductive trace layer and the conductive stud layer. The conductive stud layer is exposed. A plating conductive layer is formed to envelop the conductive carrier, the dielectric layer and the exposed end of the conductive stud layer. A cavity is formed on the conductive carrier, wherein the conductive trace layer and the dielectric layer are exposed in the cavity. A surface finishing is formed on at least an exposed portion of the conductive stud layer. The plating conductive layer is removed.
摘要翻译：提供具有第一表面和第二表面的导电载体。导电迹线层形成在导电载体的第二表面上。导电柱层形成在导电迹线层上。在导电层上形成介电层，以封装导电迹线层和导电柱层。导电柱层露出。形成电镀导电层以包围导电载体，电介质层和导电柱层的暴露端。在导电载体上形成空穴，其中导电迹线层和电介质层暴露在空腔中。在导电柱层的至少露出部分上形成表面精加工。去除电镀导电层。

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