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1. 发明授权

US06693364B2 Optical integrated circuit element package and process for making the same 有权
标题翻译：光集成电路元件封装及其制造方法
公开(公告)号：US06693364B2
公开(公告)日：2004-02-17
申请号：US10355152
申请日：2003-01-31
申请人： Su Tao , Kuo Chung Yee , Jen Chieh Kao , Chih Lung Chen , Hsing Jung Liau
发明人： Su Tao , Kuo Chung Yee , Jen Chieh Kao , Chih Lung Chen , Hsing Jung Liau
IPC分类号： H01L2348
CPC分类号： H01L31/0203 , H01L21/563 , H01L23/49816 , H01L25/0657 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/73203 , H01L2224/73253 , H01L2924/00014 , H01L2924/01079 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2224/05599
摘要： An optical integrated circuit element package comprises a substrate, an upper chip, a lower chip, an optical-transparent underfill, and a sealing compound. The substrate has a plurality of solder balls disposed on a surface of the substrate, a plurality of bonding pads electrically connected to the solder balls, a cover attached to the other surface of the substrate, and a cavity to expose the cover. The upper chip is provided with a plurality of bumps and is adhered to the exposed cover in the cavity by a thermal gap fill. The lower chip has a plurality of bonding pads electrically connected to the plurality of bumps of the upper chip and has a plurality of bumps electrically connected to the plurality of bonding pads of the substrate. The optical-transparent underfill is disposed between the lower chip and the upper chip. The sealing compound hermetically seals the space between the lower chip and the substrate.
摘要翻译：一种光学集成电路元件封装，包括衬底，上部芯片，下部芯片，光学透明底部填充物和密封化合物。衬底具有设置在衬底的表面上的多个焊球，与焊球电连接的多个接合焊盘，附接到衬底的另一个表面的盖以及露出罩的空腔。上芯片设置有多个凸块，并且通过热间隙填充而粘附到空腔中的暴露盖。下部芯片具有电连接到上部芯片的多个凸起的多个焊盘，并且具有电连接到该衬底的多个焊盘的多个凸块。光学透明底部填充物设置在下部芯片和上部芯片之间。密封组合物密封下部芯片和基板之间的空间。

2. 发明授权

US06809852B2 Microsystem package structure 有权
标题翻译：微系统封装结构
公开(公告)号：US06809852B2
公开(公告)日：2004-10-26
申请号：US10603957
申请日：2003-06-24
申请人： Su Tao , Kuo-Chung Yee , Jen-Chieh Kao , Chih-Lung Chen , Hsing-Jung Liau
发明人： Su Tao , Kuo-Chung Yee , Jen-Chieh Kao , Chih-Lung Chen , Hsing-Jung Liau
IPC分类号： G02B2600
CPC分类号： G02B7/1821 , H01L2224/16145 , H01L2224/32225 , H01L2224/73265 , H01L2924/00014 , H01L2224/0401
摘要： The present invention relates to a package structure for a microsystem, comprising a substrate, a chip, an adhesive structure, a carrying substrate, a micro-mechanism, a plurality of wires, an annular body and a transparent plate. The chip is placed on the substrate. The annular adhesive structure having an opening is placed on the chip. The carrying substrate is placed on the adhesive structure, thus forming an interspace between the chip, the adhesive structure and the carrying substrate. The pressure inside the interspace can be balanced with the pressure outside the interspace through the opening. The micro-mechanism is disposed on the carrying substrate. The annular body is formed on the substrate and the transparent plate is attached on the annular body, thus forming a closed chamber between the substrate, the annular body and the transparent plate. The chip, the micro-mechanism, the adhesive structure, the carrying substrate and the wires are disposed within the closed chamber.
摘要翻译：本发明涉及一种用于微系统的封装结构，其包括基板，芯片，粘合结构，承载基板，微机构，多根导线，环形体和透明板。将芯片放置在基板上。具有开口的环形粘合剂结构被放置在芯片上。携带衬底被放置在粘合剂结构上，从而在芯片，粘合剂结构和承载衬底之间形成间隙。间隙内的压力可以通过开口与间隙外的压力平衡。微机构设置在承载基板上。环状体形成在基板上，透明板安装在环状体上，由此在基板，环状体和透明板之间形成封闭室。芯片，微机构，粘合剂结构，承载基板和电线设置在封闭室内。

3. 发明授权

US06822324B2 Wafer-level package with a cavity and fabricating method thereof 有权
标题翻译：具有腔体的晶片级封装及其制造方法
公开(公告)号：US06822324B2
公开(公告)日：2004-11-23
申请号：US10352042
申请日：2003-01-28
申请人： Su Tao , Kuo-Chung Yee , Jen-Chieh Kao , Chih-Lung Chen , Hsing-Jung Liau
发明人： Su Tao , Kuo-Chung Yee , Jen-Chieh Kao , Chih-Lung Chen , Hsing-Jung Liau
IPC分类号： H01L2310
CPC分类号： H01L23/055 , H01L23/04 , H01L2224/05568 , H01L2224/0557 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/01079 , H01L2924/07811 , H01L2924/15311 , H01L2924/16235 , H01L2924/00 , H01L2224/05599
摘要： A wafer-level package with a cavity includes a chip, a substrate, and a seal member. The chip has a micro device and a plurality of bonding pads electrically connected to the micro device. The substrate has a plurality of through conductive vias corresponding and electrically connected to the bonding pads. Each of the bonding pads on the chip is provided with a conductive bump for electrically connecting the bonding pad to the conductive via. The seal member surrounds the package to form a hermetical cavity. The present invention further provides a method for fabricating the wafer-level package with a cavity.
摘要翻译：具有空腔的晶片级封装包括芯片，基板和密封构件。芯片具有微型器件和电连接到微器件的多个接合焊盘。衬底具有对应并电连接到接合焊盘的多个通孔导电孔。芯片上的每个接合焊盘设置有用于将焊盘电连接到导电通孔的导电凸块。密封构件围绕包装以形成密封腔。本发明还提供一种用于制造具有空腔的晶片级封装的方法。

4. 发明授权

US06768207B2 Multichip wafer-level package and method for manufacturing the same 有权
标题翻译：多芯片晶圆级封装及其制造方法
公开(公告)号：US06768207B2
公开(公告)日：2004-07-27
申请号：US10392851
申请日：2003-03-21
申请人： Su Tao , Kuo Chung Yee , Jen Chieh Kao , Chih Lung Chen , Hsing Jung Liau
发明人： Su Tao , Kuo Chung Yee , Jen Chieh Kao , Chih Lung Chen , Hsing Jung Liau
IPC分类号： H01L2348
CPC分类号： H01L25/50 , H01L23/10 , H01L24/48 , H01L25/0657 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05572 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06586 , H01L2924/00014 , H01L2924/00015 , H01L2924/01079 , H01L2924/07811 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2224/85399 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A multichip wafer-level package includes a first chip, a second chip, a bump ring and a plurality of bumps. The first chip has a semiconductor device, a first bonding ring surrounding the semiconductor device, a plurality of internal bonding pads disposed within the first bonding ring and electrically connected to the semiconductor device, and a plurality of external bonding pads disposed outside the first bonding ring and electrically connected to the semiconductor device for electrically connecting to an external circuit. The second chip has an electronic device, a plurality of bonding pads electrically connected to the electronic device and corresponding to the internal bonding pads of the first chip, and a second bonding ring corresponding to the first bonding ring of the first chip. The bump ring is disposed between the first bonding ring of the first chip and the second bonding ring of the second chip for bonding the first and the second chips so as to form a cavity for accommodating the semiconductor device. The bumps electrically connect the internal bonding pads of the first chip to the bonding pads of the second chip.
摘要翻译：多芯片晶片级封装包括第一芯片，第二芯片，凸块环和多个凸块。第一芯片具有半导体器件，围绕半导体器件的第一接合环，设置在第一接合环内并电连接到半导体器件的多个内部接合焊盘，以及设置在第一接合环外侧的多个外部接合焊盘并且电连接到半导体器件用于电连接到外部电路。第二芯片具有电子器件，电连接到电子器件并对应于第一芯片的内部接合焊盘的多个接合焊盘以及与第一芯片的第一接合环相对应的第二接合环。凸块环设置在第一芯片的第一接合环和第二芯片的第二接合环之间，用于接合第一和第二芯片，以形成用于容纳半导体器件的空腔。凸块将第一芯片的内部焊盘电连接到第二芯片的焊盘。

5. 发明授权

US06838762B2 Water-level package with bump ring 有权
标题翻译：带有凸环的水位包装
公开(公告)号：US06838762B2
公开(公告)日：2005-01-04
申请号：US10412291
申请日：2003-04-14
申请人： Su Tao , Kuo Chung Yee , Jen Chieh Kao , Chih Lung Chen , Hsing Jung Liau
发明人： Su Tao , Kuo Chung Yee , Jen Chieh Kao , Chih Lung Chen , Hsing Jung Liau
IPC分类号： B81B7/00 , H01L23/10 , H01L23/28 , H01L23/48 , H01L25/065 , H01L31/075
CPC分类号： B81B7/0041 , B81C2203/0118 , B81C2203/019 , H01L23/10 , H01L25/0657 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05572 , H01L2224/16 , H01L2225/06513 , H01L2225/06555 , H01L2225/06582 , H01L2924/01079 , H01L2924/07811 , H01L2924/09701 , H01L2924/16235 , H01L2924/00
摘要： A wafer-level package includes a first chip, a second chip and a bump ring. The first chip has a semiconductor micro device, a bonding pad ring surrounding the semiconductor micro device, and a plurality of bonding pads disposed outside the bonding pad ring and electrically connected to the semiconductor micro device for electrically connecting to an external circuit. The second chip has a bonding pad ring corresponding to the bonding pad ring of the first chip. The bump ring is disposed between the bonding pad ring of the first chip and the bonding pad ring of the second chip for bonding the first and the second chips so as to form a hermetical cavity.
摘要翻译：晶片级封装包括第一芯片，第二芯片和凸块环。第一芯片具有半导体微器件，围绕半导体微器件的焊盘环，以及设置在焊盘环外部并电连接到半导体微器件用于电连接到外部电路的多个焊盘。第二芯片具有与第一芯片的焊盘环相对应的焊盘环。凸块环设置在第一芯片的焊盘环和第二芯片的焊盘环之间，用于接合第一芯片和第二芯片以形成密封腔。

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