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1. 发明授权

US5041393A Fabrication of GaAs integrated circuits 失效
标题翻译： GaAs集成电路的制造
公开(公告)号：US5041393A
公开(公告)日：1991-08-20
申请号：US290932
申请日：1988-12-28
申请人： Richard E. Ahrens , Albert G. Baca , Randolph H. Burton , Michael P. Iannuzzi , Alex Lahav , Shin-Shem Pei , Claude L. Reynolds, Jr. , Thi-Hong-Ha Vuong
发明人： Richard E. Ahrens , Albert G. Baca , Randolph H. Burton , Michael P. Iannuzzi , Alex Lahav , Shin-Shem Pei , Claude L. Reynolds, Jr. , Thi-Hong-Ha Vuong
IPC分类号： H01L29/80 , H01L21/20 , H01L21/338 , H01L21/76 , H01L21/8252 , H01L29/778 , H01L29/812
CPC分类号： H01L21/7605 , H01L21/8252 , Y10S148/072
摘要： A process for manufacturing selectively doped heterostructure field-effect transistors (SDHTs), a desired wafer structure for SDHT fabrication and a method for isolating SDHTs on the wafer are disclosed herein. The wafer has epitaxial layers grown on a substrate. The layers are: a buffer layer of GaAs, a first spacer layer of AlGaAs, a donor layer of AlGaAs, a second spacer layer of AlGaAs, a first cap layer of GaAs, an etch-stop layer of AlGaAs and a second cap layer of GaAs. A protective layer of AlGaAs may then be grown on the second cap layer to protect the second cap layer from contamination or damage. Also a superlattice may first be grown on the substrate.This invention was made with Government support under contract No. F29601-87-R-0202 awarded by the Defense Advanced Research Projects Agency, and under contract No. F33615-84-C-1570 awarded by the Air Force Wright Aeronautical Laboratories. The Government has certain rights in this invention.

2. 发明申请

US20120304140A1 FULLY PARAMETERIZABLE REPRESENTATION OF A HIGHER LEVEL DESIGN ENTITY 有权
标题翻译：高度设计实体的全面可参考表示
公开(公告)号：US20120304140A1
公开(公告)日：2012-11-29
申请号：US13114834
申请日：2011-05-24
申请人： Shawn Boshart , Shahriar Moinian , Joshua Williams , Hong-ha Vuong
发明人： Shawn Boshart , Shahriar Moinian , Joshua Williams , Hong-ha Vuong
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5063 , G06F2217/66
摘要： A parameterizable design system is for use with semiconductor analog circuits and includes an interface unit connected to provide access to the system, a database unit connected to supply a library of parameterizable analog building blocks for a design entity, and a parameterization unit connected to select a parameter for one of the library of parameterizable analog building blocks to meet a design specification of the design entity. Additionally, the parameterizable design system may also include a simulation unit connected to simulate an operation of the design entity employing the parameter, and an analyzer unit connected to analyze a sensitivity of the parameter for the design entity based on the design specification. A method of designing a semiconductor analog circuit is also included.
摘要翻译：可参数化的设计系统与半导体模拟电路一起使用，并且包括被连接以提供对系统的访问的接口单元，连接到用于为设计实体提供可参数化的模拟构建块的库的数据库单元，以及连接以选择一个参数为可参数化的模拟构建块之一，以满足设计实体的设计规范。此外，可参数化设计系统还可以包括连接以模拟使用参数的设计实体的操作的模拟单元，以及连接以基于设计规范分析设计实体的参数的灵敏度的分析器单元。还包括设计半导体模拟电路的方法。

3. 发明授权

US6054342A Method of making integrated circuits with tub-ties 有权
标题翻译：制造集成电路的方法
公开(公告)号：US6054342A
公开(公告)日：2000-04-25
申请号：US339306
申请日：1999-06-23
申请人： Hans-Joachim Ludwig Gossmann , Thi-Hong-Ha Vuong
发明人： Hans-Joachim Ludwig Gossmann , Thi-Hong-Ha Vuong
IPC分类号： H01L21/266 , H01L21/761 , H01L21/762 , H01L21/8238
CPC分类号： H01L21/76202 , H01L21/266 , H01L21/761 , H01L21/76218 , H01L21/823892
摘要： An IC comprises a tub of a first conductivity type, at least one transistor embedded in the tub, and a first pair of isolating regions defining therebetween a tub-tie region coupled to the tub. The tub-tie region comprises a cap portion of the first conductivity type and an underlying buried pedestal portion of a second conductivity type. At least a top section of the pedestal portion is surrounded by the cap portion so that a conducting path is formed between the cap portion and the tub. In a CMOS IC tub-ties of this design are provided for both NMOS and PMOS transistors. In a preferred embodiment, the cap portion of each tub-tie comprises a relatively heavily doped central section and more lightly doped peripheral sections, both of the same conductivity type.In accordance with another aspect of our invention, a reduced-mask-count CMOS IC process includes forming the isolating regions so that each has a protrusion which extends over the surface regions where the peripheral sections of the cap portion are to be formed. Then, a combination of ion implantation energies and concentrations, as well as suitable PR masking, in conjunction with the shape of the isolating regions, enables selective doping of the pedestal portion.
摘要翻译： IC包括第一导电类型的桶，嵌入在桶中的至少一个晶体管，以及第一对隔离区域，其中限定了耦合到桶的桶连接区域。连接区域包括第一导电类型的盖部分和第二导电类型的下面的埋入基座部分。基座部分的至少顶部被盖部分围绕，使得在盖部分和桶之间形成导电路径。在这种设计的CMOS IC管中，为NMOS和PMOS晶体管提供。在一个优选实施例中，每个桶带的盖部分包括相对重掺杂的中心部分和更多轻掺杂的外围部分，两者都是相同的导电类型。根据本发明的另一方面，减少掩模计数的CMOS IC工艺包括形成隔离区域，使得每个隔离区域都具有在要形成盖部分的周边部分的表面区域上延伸的突起。然后，结合隔离区域的形状，离子注入能量和浓度的组合以及合适的PR掩模能够选择性地掺杂基座部分。

4. 发明授权

US5949112A Integrated circuits with tub-ties 失效
标题翻译：集成电路与管道
公开(公告)号：US5949112A
公开(公告)日：1999-09-07
申请号：US85913
申请日：1998-05-28
申请人： Hans-Joachim Ludwig Gossmann , Thi-Hong-Ha Vuong
发明人： Hans-Joachim Ludwig Gossmann , Thi-Hong-Ha Vuong
IPC分类号： H01L21/266 , H01L21/761 , H01L21/762 , H01L21/8238 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/76202 , H01L21/266 , H01L21/761 , H01L21/76218 , H01L21/823892
摘要： An IC comprises a tub of a first conductivity type, at least one transistor embedded in the tub, and a first pair of isolating regions defining therebetween a tub-tie region coupled to the tub. The tub-tie region comprises a cap portion of the first conductivity type and an underlying buried pedestal portion of a second conductivity type. At least a top section of the pedestal portion is surrounded by the cap portion so that a conducting path is formed between the cap portion and the tub. In a CMOS IC tub-ties of this design are provided for both NMOS and PMOS transistors. In a preferred embodiment, the cap portion of each tub-tie comprises a relatively heavily doped central section and more lightly doped peripheral sections, both of the same conductivity type. In accordance with another aspect of our invention, a reduced-mask-count CMOS IC process includes forming the isolating regions so that each has a protrusion which extends over the surface regions where the peripheral sections of the cap portion are to be formed. Then, a combination of ion implantation energies and concentrations, as well as suitable PR masking, in conjunction with the shape of the isolating regions, enables selective doping of the pedestal portion.
摘要翻译： IC包括第一导电类型的桶，嵌入在桶中的至少一个晶体管，以及第一对隔离区域，其中限定了耦合到桶的桶连接区域。连接区域包括第一导电类型的盖部分和第二导电类型的下面的埋入基座部分。基座部分的至少顶部被盖部分围绕，使得在盖部分和桶之间形成导电路径。在这种设计的CMOS IC管中，为NMOS和PMOS晶体管提供。在一个优选实施例中，每个桶带的盖部分包括相对重掺杂的中心部分和更多轻掺杂的外围部分，两者都是相同的导电类型。根据本发明的另一方面，减少掩模计数的CMOS IC工艺包括形成隔离区域，使得每个隔离区域都具有在要形成盖部分的周边部分的表面区域上延伸的突起。然后，结合隔离区域的形状，离子注入能量和浓度的组合以及合适的PR掩模能够选择性地掺杂基座部分。

5. 发明授权

US07768044B2 Metal capacitor stacked with a MOS capacitor to provide increased capacitance density 有权
标题翻译：金属电容器堆叠有MOS电容器以提供增加的电容密度
公开(公告)号：US07768044B2
公开(公告)日：2010-08-03
申请号：US10903938
申请日：2004-07-30
申请人： Canzhong He , John A. Schuler , John M. Sharpe , Hong-Ha Vuong
发明人： Canzhong He , John A. Schuler , John M. Sharpe , Hong-Ha Vuong
IPC分类号： H01L29/76 , H01L29/94 , H01L21/20 , H01L21/336 , H01L21/8234
CPC分类号： H01L28/86 , H01L23/5223 , H01L27/0207 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： An on-chip capacitive device comprises a semiconductor substrate, a MOS capacitor formed on the semiconductor substrate, and a metal interconnect capacitor formed at least in part in a region above the MOS capacitor. The MOS capacitor and the metal interconnect capacitor are connected in parallel to form a single capacitive device. The capacitance densities of the MOS capacitor and the metal interconnect capacitor are, thereby, combined. Advantageously, significant capacitance density gains can be achieved without additional processing steps.
摘要翻译：片上电容器件包括半导体衬底，形成在半导体衬底上的MOS电容器和至少部分地形成在MOS电容器上方的金属互连电容器。 MOS电容器和金属互连电容器并联连接以形成单个电容器件。因此，MOS电容器和金属互连电容器的电容密度被组合。有利地，可以在没有额外的处理步骤的情况下实现显着的电容密度增益。

6. 发明申请

US20060024905A1 Metal capacitor stacked with a MOS capacitor to provide increased capacitance density 有权
标题翻译：金属电容器堆叠有MOS电容器以提供增加的电容密度
公开(公告)号：US20060024905A1
公开(公告)日：2006-02-02
申请号：US10903938
申请日：2004-07-30
申请人： Canzhong He , John Schuler , John Sharpe , Hong-Ha Vuong
发明人： Canzhong He , John Schuler , John Sharpe , Hong-Ha Vuong
IPC分类号： H01L21/20
CPC分类号： H01L28/86 , H01L23/5223 , H01L27/0207 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： An on-chip capacitive device comprises a semiconductor substrate, a MOS capacitor formed on the semiconductor substrate, and a metal interconnect capacitor formed at least in part in a region above the MOS capacitor. The MOS capacitor and the metal interconnect capacitor are connected in parallel to form a single capacitive device. The capacitance densities of the MOS capacitor and the metal interconnect capacitor are, thereby, combined. Advantageously, significant capacitance density gains can be achieved without additional processing steps.
摘要翻译：片上电容器件包括半导体衬底，形成在半导体衬底上的MOS电容器和至少部分地形成在MOS电容器上方的金属互连电容器。 MOS电容器和金属互连电容器并联连接以形成单个电容器件。因此，MOS电容器和金属互连电容器的电容密度被组合。有利地，可以在没有额外的处理步骤的情况下实现显着的电容密度增益。

7. 发明授权

US08464202B2 Fully parameterizable representation of a higher level design entity 有权
标题翻译：高级设计实体的全参数化表示
公开(公告)号：US08464202B2
公开(公告)日：2013-06-11
申请号：US13114834
申请日：2011-05-24
申请人： Shawn Boshart , Shahriar Moinian , Joshua Williams , Hong-Ha Vuong
发明人： Shawn Boshart , Shahriar Moinian , Joshua Williams , Hong-Ha Vuong
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5063 , G06F2217/66
摘要： A parameterizable design system is for use with semiconductor analog circuits and includes an interface unit connected to provide access to the system, a database unit connected to supply a library of parameterizable analog building blocks for a design entity, and a parameterization unit connected to select a parameter for one of the library of parameterizable analog building blocks to meet a design specification of the design entity. Additionally, the parameterizable design system may also include a simulation unit connected to simulate an operation of the design entity employing the parameter, and an analyzer unit connected to analyze a sensitivity of the parameter for the design entity based on the design specification. A method of designing a semiconductor analog circuit is also included.
摘要翻译：可参数化的设计系统与半导体模拟电路一起使用，并且包括被连接以提供对系统的访问的接口单元，连接到用于为设计实体提供可参数化的模拟构建块的库的数据库单元，以及连接以选择一个参数为可参数化的模拟构建块之一，以满足设计实体的设计规范。此外，可参数化设计系统还可以包括连接以模拟使用参数的设计实体的操作的模拟单元，以及连接以基于设计规范分析设计实体的参数的灵敏度的分析器单元。还包括设计半导体模拟电路的方法。

8. 发明授权

US06358824B1 Integrated circuits with tub-ties and shallow trench isolation 有权
标题翻译：集成电路具有管状和浅沟槽隔离
公开(公告)号：US06358824B1
公开(公告)日：2002-03-19
申请号：US09706319
申请日：2000-11-03
申请人： Hans-Joachim Ludwig Gossmann , Thi-Hong-Ha Vuong
发明人： Hans-Joachim Ludwig Gossmann , Thi-Hong-Ha Vuong
IPC分类号： H01L21425
CPC分类号： H01L21/76237 , H01L21/823878
摘要： A method of fabricating an IC comprises the steps of: (a) forming trench isolation regions in a surface of a semiconductor body; and (b) forming a tub-tie region between at least one pair of the trench isolation regions (when viewed in cross-section) by a process that includes the following steps: (b1) forming a first photolithographic mask that covers and is in registration with the tub-tie region; (b2) implanting ions of a first conductivity-type to form a tub region adjacent the tub-tie region; (b3) removing the first mask; (b4) forming a second photolithographic mask that has an opening that exposes most of the underlying tub-tie region but overlaps a first peripheral section on one side of the tub-tie region; (b5) implanting ions to form a pedestal portion of a second conductivity-type within the tub-tie region; and (b6) implanting ions of the first conductivity-type at an acute (preferably non-zero) angle −⊕ with respect to the normal to the surface to the body so as to form a conductivity-type localized first zone that extends into the first peripheral section. In a preferred embodiment, the first conductivity-type tub of step (b2) and the second conductivity-type pedestal of step (b5) are formed by implanting ions at an acute (non-zero) angle +&bgr; to the normal to the surface of the body. In another embodiment, between steps (b1) and (b3), the cap portion is angle-implanted to form a highly doped peripheral localized second zone of the second conductivity type located adjacent a different portion of one of said isolating regions. The second zone prevents any significant amount of charge build-up from taking place in the pedestal portion.
摘要翻译：一种制造IC的方法包括以下步骤：（a）在半导体本体的表面中形成沟槽隔离区; 和（b）在至少一对沟槽隔离区域之间（当横截面观察时）通过包括以下步骤的工艺形成管连接区域：（b1）形成覆盖并处于其中的第一光刻掩模与领带区域注册; （b2）注入第一导电类型的离子以形成与所述连接区相邻的盆区; （b3）去除第一掩模; （b4）形成第二光刻掩模，所述第二光刻掩模具有暴露所述下面的连接区域中的大部分但与所述连接区域的一侧上的第一外围部分重叠的开口; （b5）植入离子以在所述连接区域内形成第二导电类型的基座部分; 和（b6）将第一导电类型的离子相对于表面的法线相对于身体的锐角（优选非零）角度）注入，以便形成导电类型的局部第一区，其延伸到第一个周边部分。在优选实施例中，步骤（b2）的第一导电型桶和步骤（b5）的第二导电型基座通过以与表面法线成锐角（非零）角度+β的离子注入而形成的身体。在另一个实施例中，在步骤（b1）和（b3）之间，帽部分是角度注入的，以形成位于邻近所述隔离区域之一的不同部分的第二导电类型的高度掺杂的外围局部第二区域。第二区域防止在基座部分中发生任何显着量的电荷积聚。

9. 发明授权

US06316809B1 Analog MOSFET devices 有权
标题翻译：模拟MOSFET器件
公开(公告)号：US06316809B1
公开(公告)日：2001-11-13
申请号：US09226378
申请日：1999-01-06
申请人： Ali Eshraghi , Venugopal Gopinathan , John Michael Khoury , Maurice J. Tarsia , Thi-Hong-Ha Vuong
发明人： Ali Eshraghi , Venugopal Gopinathan , John Michael Khoury , Maurice J. Tarsia , Thi-Hong-Ha Vuong
IPC分类号： H01L29772
CPC分类号： H01L29/6659 , H01L29/1045 , H01L29/1083 , H01L29/7833
摘要： The specification describes MOS transistors for analog functions which have increased output impedance. The increased output impedance is the result of reduced drain depletion width. This is accomplished without adverse effects on other device parameters. The MOS transistor structures have an implant added to the lightly doped drain (LDD) with a conductivity type opposite to that of the LDD and a doping level higher than the channel doping. The added implant confines the spread of the depletion layer and reduces its width. A relatively small confinement results in a significant increase in output impedance of the device, and a corresponding increase in transistor gain.
摘要翻译：该规范描述了具有增加的输出阻抗的模拟功能的MOS晶体管。增加的输出阻抗是减少漏极耗尽宽度的结果。这是完成的，而不会对其他设备参数产生不利影响。 MOS晶体管结构具有添加到具有与LDD相反的导电类型的掺杂稀土漏极（LDD）的注入和高于沟道掺杂的掺杂水平的注入。添加的植入物限制耗尽层的扩展并减小其宽度。相对较小的限制导致器件的输出阻抗显着增加，并且晶体管增益相应增加。

10. 发明授权

US6136673A Process utilizing selective TED effect when forming devices with shallow junctions 失效
标题翻译：当形成具有浅结的器件时，利用选择性TED效应的工艺
公开(公告)号：US6136673A
公开(公告)日：2000-10-24
申请号：US23220
申请日：1998-02-12
申请人： Michel Ranjit Frei , Thi-Hong-Ha Vuong , Ya-Hong Xie
发明人： Michel Ranjit Frei , Thi-Hong-Ha Vuong , Ya-Hong Xie
IPC分类号： H01L21/22 , H01L21/225 , H01L21/265 , H01L21/331 , H01L21/8249
CPC分类号： H01L29/66272 , H01L21/2257 , H01L21/26506 , H01L21/8249
摘要： A process for device fabrication in which transient enhanced diffusion (TED) is used to obtain a desired distribution of dopants in a crystalline substrate is disclosed. In the process, at least two dopants and a non-dopant are introduced into the same region of a substrate. The diffusion of the dopants in the substrate during a subsequent thermal anneal is affected by the non-dopant. The amount of non-dopant introduced into the substrate is selected to obtain, in conjunction with the subsequent thermal anneal, the desired distribution of dopants in the substrate. The concentration of the non-dopant is in the range of about 6.times.10.sup.16 atoms/cm.sup.3 to about 3.times.10.sup.21 atoms/cm.sup.3. The substrate is then annealed at a temperature in the range of about 700.degree. C. to about 950.degree. C. to obtain the desired dopant profile.
摘要翻译：公开了一种用于器件制造的方法，其中使用瞬态增强扩散（TED）来获得晶体衬底中掺杂剂的期望分布。在该过程中，将至少两种掺杂剂和非掺杂剂引入衬底的相同区域。在随后的热退火期间掺杂剂在衬底中的扩散受非掺杂剂的影响。选择引入到衬底中的非掺杂剂的量，以结合随后的热退火获得衬底中掺杂剂的期望分布。非掺杂剂的浓度在约6×1016原子/ cm3至约3×1021原子/ cm3的范围内。然后将衬底在约700℃至约950℃的温度下退火，以获得所需的掺杂剂分布。

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