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    • 2. 发明申请
    • Cryptographic unit and method for operating a cryptographic unit
    • 用于操作加密单元的加密单元和方法
    • US20070189536A1
    • 2007-08-16
    • US11318061
    • 2005-12-23
    • Berndt GammelHolger BockMichael Goessel
    • Berndt GammelHolger BockMichael Goessel
    • H04L9/00
    • H04L9/0631H04L9/004H04L2209/12
    • A cryptographic unit includes a first processing unit for determining an output signal on the basis of the AES algorithm and for determining a first comparison signal, a second processing unit for determining a second comparison signal, and a release unit for providing the output signal, wherein the release unit is designed to perform a defense measure against an external tapping of the output signal when the first comparison signal is not related to the second comparison signal in a predetermined relationship. The first comparison signal is determined in a different way as compared to the second comparison signal, so that, in the case of the injection of faults into the cryptographic unit, these faults may be detected very easily.
    • 密码单元包括:第一处理单元,用于基于AES算法确定输出信号,并确定第一比较信号;第二处理单元,用于确定第二比较信号;以及释放单元,用于提供输出信号,其中, 释放单元被设计成当第一比较信号与预定关系中的第二比较信号无关时,执行针对输出信号的外部抽头的防御措施。 与第二比较信号相比,以不同的方式确定第一比较信号,使得在将故障注入密码单元的情况下,可以非常容易地检测到这些故障。
    • 10. 发明申请
    • Logic circuit
    • 逻辑电路
    • US20050134319A1
    • 2005-06-23
    • US11018404
    • 2004-12-20
    • Holger Bock
    • Holger Bock
    • H03K5/151H03K19/003H03K19/23H03K19/20
    • H03K5/151H03K19/00323
    • A logic circuit includes an input for one or several input operands, an output for a result and an inverted result, a first circuit branch with a first logic assembly, which is coupled to the input and the output, to calculate the result, as well as a second circuit branch with a second logic assembly, which is coupled to the input and the output, to calculate the inverted result, wherein the first logic assembly and the second logic assembly have different run times for calculating the result and the inverted result, respectively. Further, a delay circuit and a compensation circuit, respectively, are provided in the first and/or second circuit branch to reduce a difference of the run times and the power consumptions, respectively, of the first and the second circuit branch.
    • 逻辑电路包括用于一个或几个输入操作数的输入,用于结果的输出和反相结果,具有第一逻辑组件的第一电路分支,其耦合到输入和输出,以计算结果 作为具有第二逻辑组件的第二电路分支,其耦合到输入和输出以计算反相结果,其中第一逻辑组件和第二逻辑组件具有用于计算结果和反相结果的不同运行时间, 分别。 此外,分别在第一和/或第二电路支路中提供延迟电路和补偿电路,以分别减小第一和第二电路支路的运行时间和功率消耗的差异。