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1. 发明申请

US20160055056A1 MEMORY DEVICE HAVING ERROR NOTIFICATION FUNCTION 有权
标题翻译：具有错误通知功能的存储器
公开(公告)号：US20160055056A1
公开(公告)日：2016-02-25
申请号：US14729656
申请日：2015-06-03
申请人： Jong-Pil SON , Chul-Woo PARK , Seong-Jin JANG , Hoi-Ju CHUNG , Sang-Uhn CHA
发明人： Jong-Pil SON , Chul-Woo PARK , Seong-Jin JANG , Hoi-Ju CHUNG , Sang-Uhn CHA
IPC分类号： G06F11/10 , G11C29/52
CPC分类号： G06F11/1008 , G06F11/1004 , G06F11/1024 , G06F11/1068 , G06F11/1666 , G11C2029/0411
摘要： A memory device having an error notification function includes an error correction code (ECC) engine detecting and correcting an error bit by performing an ECC operation on data of the plurality of memory cells, and an error notifying circuit configured to output an error signal according to the ECC operation. The ECC engine outputs error information corresponding to the error bit corresponding to a particular address corrected by the ECC operation. The error notifying circuit may output the error signal when the particular address is not the same as any one of existing one or more failed addresses.
摘要翻译：具有错误通知功能的存储装置包括通过对多个存储单元的数据执行ECC操作来检测和校正错误位的纠错码（ECC）引擎，以及错误通知电路，配置为根据 ECC操作。 ECC引擎输出与通过ECC操作校正的特定地址相对应的错误位对应的错误信息。当特定地址与现有一个或多个故障地址中的任一个不同时，错误通知电路可以输出错误信号。

2. 发明申请

US20160062830A1 SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHOD OF CORRECTING ERRORS IN THE SAME 有权
标题翻译：半导体存储器件，包括其的存储器系统和校正其中的错误的方法
公开(公告)号：US20160062830A1
公开(公告)日：2016-03-03
申请号：US14729295
申请日：2015-06-03
申请人： Sang-Uhn CHA , Hoi-Ju CHUNG , Jong-Pil SON , Kwang-Il PARK , Seong-Jin JANG
发明人： Sang-Uhn CHA , Hoi-Ju CHUNG , Jong-Pil SON , Kwang-Il PARK , Seong-Jin JANG
IPC分类号： G06F11/10 , G11C29/52
CPC分类号： G11C29/52 , G06F11/1048 , G11C11/15 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C29/702 , G11C2029/0411 , G11C2029/4402
摘要： A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.
摘要翻译：半导体存储器件包括其中布置有多个存储器单元的存储单元阵列。半导体存储器件包括：纠错码（ECC）电路，被配置为基于主数据产生奇偶校验数据，将包括主数据和奇偶校验数据的码字写入存储单元阵列，将所选择的存储单元行的码字读取到产生综合征，并且基于每个符号基于综合征来校正读取的码字中的错误。主数据包括所选存储单元行的第一存储单元的第一数据和所选存储单元行的第二存储单元的第二数据。将第一数据和第二数据分配给多个符号的一个符号，并且第一存储单元和第二存储单元在存储单元阵列中彼此相邻。

3. 发明申请

US20110267876A1 NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT 有权
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：US20110267876A1
公开(公告)日：2011-11-03
申请号：US13085453
申请日：2011-04-12
申请人： Byung-Jun MIN , Hoi-Ju CHUNG
发明人： Byung-Jun MIN , Hoi-Ju CHUNG
IPC分类号： G11C11/00 , G11C29/04
CPC分类号： G11C8/12 , G11C13/0004 , G11C29/80 , G11C29/846
摘要： A nonvolatile memory device that employs a variable resistive element includes: a memory cell array having a plurality of memory cells; a first circuit block that is disposed at one side of the memory cell array and performs a first operation on the memory cells; a second circuit block that is disposed at the other side of the memory cell array and performs a second operation on the memory cells, wherein the second operation is different from the first operation; and a redundancy block that is disposed closer to the second circuit block than the first circuit block, and which compares a repair address of a repaired memory cell among the plurality of memory cells with an input address to then generate a redundancy control signal, and to supply the redundancy control signal to the first circuit block and the second circuit block.
摘要翻译：采用可变电阻元件的非易失性存储器件包括：具有多个存储单元的存储单元阵列; 第一电路块，设置在所述存储单元阵列的一侧，并对所述存储单元执行第一操作; 第二电路块，设置在存储单元阵列的另一侧，并对存储单元执行第二操作，其中第二操作与第一操作不同; 以及与第一电路块相比更靠近第二电路块设置的冗余块，并且将多个存储单元中的修复存储单元的修复地址与输入地址进行比较，然后生成冗余控制信号，并且将冗余控制信号提供给第一电路块和第二电路块。

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