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1. 发明申请

US20080002804A1 Mode register set circuit 失效
标题翻译：模式寄存器集电路
公开(公告)号：US20080002804A1
公开(公告)日：2008-01-03
申请号：US11646428
申请日：2006-12-28
申请人： Hoe-Kwon Jeong
发明人： Hoe-Kwon Jeong
IPC分类号： G11C19/00
CPC分类号： G11C7/1045 , G11C7/20 , G11C17/18
摘要： A semiconductor memory device includes a mode register set circuit having a changeable default value. The mode register set circuit, the default value of which is changeable, includes a signal input unit for latching an input signal, a storage unit driven by an initializing signal for setting the default value to a logic high or low state as required, and an output unit for latching an output of the storage unit.
摘要翻译：半导体存储器件包括具有可变的默认值的模式寄存器组电路。其默认值可变的模式寄存器设置电路包括用于锁存输入信号的信号输入单元，由初始化信号驱动的存储单元，用于根据需要将默认值设置为逻辑高或低状态;以及输出单元，用于锁存存储单元的输出。

2. 发明授权

US07724594B2 Leakage current control device of semiconductor memory device 失效
标题翻译：半导体存储器件泄漏电流控制装置
公开(公告)号：US07724594B2
公开(公告)日：2010-05-25
申请号：US12044484
申请日：2008-03-07
申请人： Sung Soo Xi , Chae Kyu Jang , Hoe Kwon Jeong
发明人： Sung Soo Xi , Chae Kyu Jang , Hoe Kwon Jeong
IPC分类号： G11C7/20 , G11C7/12
CPC分类号： G11C11/419 , G11C7/12 , G11C11/4094
摘要： A leakage current control device of a semiconductor memory device is provided to effectively remove leakage current flowing from a bit line to a word line when a process defect is generated by gate residues of the semiconductor memory device, thereby reducing unnecessary current consumption. In the leakage current control device, the bit line boosted to a voltage level of core voltage/2 is controlled at a ground voltage level during a precharge period to remove unnecessary leakage current flowing from the bit line to a word line bridge.
摘要翻译：提供半导体存储器件的漏电流控制装置，用于当通过半导体存储器件的栅极残留产生工艺缺陷时，有效地去除从位线流向字线的漏电流，从而减少不必要的电流消耗。在泄漏电流控制装置中，在预充电期间将升压到芯电压/ 2的电压电平的位线控制在接地电压电平，以去除从位线流向字线桥的不必要的漏电流。

3. 发明授权

US07746122B2 Input buffer for semiconductor memory apparatus 失效
标题翻译：半导体存储装置的输入缓冲器
公开(公告)号：US07746122B2
公开(公告)日：2010-06-29
申请号：US11637081
申请日：2006-12-12
申请人： Hoe Kwon Jeong
发明人： Hoe Kwon Jeong
IPC分类号： H03K3/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/109
摘要： Disclosed are an input buffer, and more particularly, a technique that is capable of improving the operation speed of the input buffer by improving response speed with respect to an input signal. The input buffer includes a buffer unit that operates when an activation control signal is activated, compares the voltage of an input signal to a preset reference voltage, and outputs the result of the comparison to an output node, a driving unit that performs driving control on an output of the buffer unit, and outputs an output signal, and a pull-down control unit that outputs a pull-down control signal that has a high pulse for a predetermined time when transition of a potential of the input signal occurs.
摘要翻译：公开了一种输入缓冲器，更具体地，涉及一种能够通过改善对输入信号的响应速度来提高输入缓冲器的操作速度的技术。输入缓冲器包括缓冲单元，当激活控制信号被激活时，该缓冲器单元将输入信号的电压与预设参考电压进行比较，并将比较结果输出到输出节点，对驱动单元进行驱动控制缓冲单元的输出，并输出输出信号;以及下拉控制单元，其在输入信号的电位转变发生时输出具有高脉冲的下拉控制信号达预定时间。

4. 发明授权

US07570729B2 Mode register set circuit 失效
标题翻译：模式寄存器集电路
公开(公告)号：US07570729B2
公开(公告)日：2009-08-04
申请号：US11646428
申请日：2006-12-28
申请人： Hoe-Kwon Jeong
发明人： Hoe-Kwon Jeong
IPC分类号： G11C19/00 , H03K3/356 , H03K3/12
CPC分类号： G11C7/1045 , G11C7/20 , G11C17/18
摘要： A semiconductor memory device includes a mode register set circuit having a changeable default value. The mode register set circuit, the default value of which is changeable, includes a signal input unit for latching an input signal, a storage unit driven by an initializing signal for setting the default value to a logic high or low state as required, and an output unit for latching an output of the storage unit.
摘要翻译：半导体存储器件包括具有可变的默认值的模式寄存器组电路。其默认值可变的模式寄存器设置电路包括用于锁存输入信号的信号输入单元，由初始化信号驱动的存储单元，用于根据需要将默认值设置为逻辑高或低状态;以及输出单元，用于锁存存储单元的输出。

5. 发明申请

US20080056038A1 Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20080056038A1
公开(公告)日：2008-03-06
申请号：US11819817
申请日：2007-06-26
申请人： Hoe-Kwon Jeong
发明人： Hoe-Kwon Jeong
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C7/12 , G11C7/1045 , G11C7/22 , G11C11/4076 , G11C11/4094
摘要： A semiconductor memory device is able to control a timing of an auto-precharge operation. The semiconductor memory device includes a timing controller and an auto-precharge controller. The timing controller generates timing control signals to be used for controlling a timing of an auto-precharge operation based on control signals inputted from an external device or through a mode register set. The auto-precharge controller controls the auto-precharge operation in response to the timing control signals.
摘要翻译：半导体存储器件能够控制自动预充电操作的定时。半导体存储器件包括定时控制器和自动预充电控制器。定时控制器基于从外部设备输入的控制信号或通过模式寄存器组产生用于控制自动预充电操作的定时的定时控制信号。自动预充电控制器响应于定时控制信号控制自动预充电操作。

6. 发明申请

US20070188200A1 Input buffer for semiconductor memory apparatus 失效
标题翻译：半导体存储装置的输入缓冲器
公开(公告)号：US20070188200A1
公开(公告)日：2007-08-16
申请号：US11637081
申请日：2006-12-12
申请人： Hoe Kwon Jeong
发明人： Hoe Kwon Jeong
IPC分类号： H03B1/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/109
摘要： Disclosed are an input buffer, and more particularly, a technique that is capable of improving the operation speed of the input buffer by improving response speed with respect to an input signal. The input buffer includes a buffer unit that operates when an activation control signal is activated, compares the voltage of an input signal to a preset reference voltage, and outputs the result of the comparison to an output node, a driving unit that performs driving control on an output of the buffer unit, and outputs an output signal, and a pull-down control unit that outputs a pull-down control signal that has a high pulse for a predetermined time when transition of a potential of the input signal occurs.
摘要翻译：公开了一种输入缓冲器，更具体地，涉及一种能够通过改善对输入信号的响应速度来提高输入缓冲器的操作速度的技术。输入缓冲器包括缓冲单元，当激活控制信号被激活时，该缓冲器单元将输入信号的电压与预设参考电压进行比较，并将比较结果输出到输出节点，对驱动单元进行驱动控制缓冲单元的输出，并输出输出信号;以及下拉控制单元，其在输入信号的电位转变发生时输出具有高脉冲的下拉控制信号达预定时间。

7. 发明申请

US20080151662A1 LEAKAGE CURRENT CONTROL DEVICE OF SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件漏电流控制器件
公开(公告)号：US20080151662A1
公开(公告)日：2008-06-26
申请号：US12044484
申请日：2008-03-07
申请人： Sung Soo XI , Chae Kyu Jang , Hoe Kwon Jeong
发明人： Sung Soo XI , Chae Kyu Jang , Hoe Kwon Jeong
IPC分类号： G11C7/02
CPC分类号： G11C11/419 , G11C7/12 , G11C11/4094
摘要： A leakage current control device of a semiconductor memory device is provided to effectively remove leakage current flowing from a bit line to a word line when a process defect is generated by gate residues of the semiconductor memory device, thereby reducing unnecessary current consumption. In the leakage current control device, the bit line boosted to a voltage level of core voltage/2 is controlled at a ground voltage level during a precharge period to remove unnecessary leakage current flowing from the bit line to a word line bridge.
摘要翻译：提供半导体存储器件的漏电流控制装置，用于当通过半导体存储器件的栅极残留产生工艺缺陷时，有效地去除从位线流向字线的漏电流，从而减少不必要的电流消耗。在泄漏电流控制装置中，在预充电期间将升压到芯电压/ 2的电压电平的位线控制在接地电压电平，以去除从位线流向字线桥的不必要的漏电流。

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