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    • 3. 发明申请
    • TEST SOCKET
    • 测试插座
    • US20090075514A1
    • 2009-03-19
    • US12204179
    • 2008-09-04
    • Hitoshi SaitohMakoto Tsuji
    • Hitoshi SaitohMakoto Tsuji
    • H01R13/64
    • H01R12/88H01R13/627H01R2201/20
    • Provided is a test socket capable of being used more flexibly for solid-state image pickup devices of different shapes and of performing locating of the solid-state image pickup devices more precisely. The test socket houses a tested device which is a solid-state image pickup device while a test is being performed. The test socket comprises: first locating means for locating the tested device in an X direction parallel to a ceiling plane of the tested device in a housed state; urging means for urging the first locating means in a Z direction perpendicular to the ceiling plane of the tested device in the housed state; and position setting means for setting an upper limit of movement in the Z direction of the first locating means caused by the urging means to set a position in the Z direction of the first locating means relative to the tested device.
    • 提供了能够更灵活地用于不同形状的固态图像拾取装置并且更精确地执行固态图像拾取装置的定位的测试插座。 测试插座容纳被测试的设备,该测试设备是正在执行测试的固态图像拾取设备。 测试插座包括:第一定位装置,用于在被容纳的状态下将测试装置定位在平行于被测试装置的顶板平面的X方向上; 推压装置,用于在收纳状态下沿垂直于被测试装置的天花板平面的Z方向推压第一定位装置; 以及位置设定装置,用于设定由所述推动装置引起的所述第一定位装置的Z方向的移动上限,以相对于所述被测试装置来设定所述第一定位装置的Z方向的位置。
    • 9. 发明授权
    • Self test circuit for a semiconductor intergrated circuit
    • 半导体集成电路自检电路
    • US07730374B2
    • 2010-06-01
    • US11555524
    • 2006-11-01
    • Massahiro FusumadaHitoshi SaitohShinji TogashiAkira Yano
    • Massahiro FusumadaHitoshi SaitohShinji TogashiAkira Yano
    • G01R31/28
    • G01R31/31725G01R31/3187
    • A semiconductor integrated circuit that self-tests the skew margin of the clock and data signals in an LVDS. A clock signal CKB1 is held in flip-flop circuit 105 synchronously with checking clock signal A1. Checking pattern signal PAT_A is held in flip-flop circuit 104 synchronously with checking clock signal A2. When the skew margin of clock signal CKA_IN and data signal DA_IN are checked, the checking signal TCKA of flip-flop circuit 105 is input instead of clock signal CKA_IN, and the checking signal TDA of flip-flop circuit 104 is input instead of clock signal DA_IN. The timing relationship between clock signal CKB7 and checking timing signal A1 and the timing relationship between clock signal CKB7 and checking timing signal A2 are controlled independently by timing control circuit 109.
    • 一种半导体集成电路,可以自我测试LVDS中时钟和数据信号的偏移余量。 时钟信号CKB1与检查时钟信号A1同步地保持在触发器电路105中。 检查模式信号PAT_A与检查时钟信号A2同步地保持在触发器电路104中。 当检查时钟信号CKA_IN和数据信号DA_IN的偏斜边缘时,输入触发器电路105的检查信号TCKA而不是时钟信号CKA_IN,并且输入触发器电路104的检查信号TDA而不是时钟信号 DA_IN。 定时控制电路109独立地控制时钟信号CKB7与检查定时信号A1之间的时序关系以及时钟信号CKB7与检查定时信号A2之间的定时关系。