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    • 2. 发明授权
    • Hetero-junction bipolar transistor
    • 异质结双极晶体管
    • US5719415A
    • 1998-02-17
    • US615430
    • 1996-03-14
    • Motoji YaguraJohn Kevin TwynamHiroya SatoToshiaki KinosadaKoken Yoshikawa
    • Motoji YaguraJohn Kevin TwynamHiroya SatoToshiaki KinosadaKoken Yoshikawa
    • H01L29/73H01L21/331H01L29/423H01L29/45H01L29/737H01L31/0328
    • H01L29/7371H01L29/42304H01L29/452
    • A hetero-junction bipolar transistor includes: a substrate; a first conductive type collector layer disposed on the substrate; a second conductive type base layer having an external base region; and a first conductive type emitter layer having a bandgap larger than the bandgap of the base layer disposed in this order, wherein the emitter layer includes a first emitter layer, an etching stop layer, and a second emitter layer disposed in this order starting from the substrate side; a base electrode is formed on the etching stop layer or the first emitter layer disposed on the external base region; a region of the first emitter layer on the base layer has a thickness such that the region is substantially depleted at all voltages applied when the transistor is normally operated; the second emitter layer has an electron affinity equal to or smaller than an electron affinity of the first emitter layer; and the etching stop layer has an electron affinity larger than the electron affinity of the first emitter layer, and has a thickness of approximately 3 nm.
    • 异质结双极晶体管包括:基板; 设置在所述基板上的第一导电型集电极层; 具有外部基极区域的第二导电型基极层; 以及第一导电型发射极层,其具有比该基底层的带隙大的带隙,其顺次设置,其中,发射极层包括第一发射极层,蚀刻停止层和从该 基板侧; 在蚀刻停止层或设置在外部基极区上的第一发射极层上形成基极; 基极层上的第一发射极层的区域具有使得当晶体管正常工作时所施加的所有电压的区域基本上被耗尽的厚度; 第二发射极层的电子亲和力等于或小于第一发射极层的电子亲和力; 并且蚀刻停止层的电子亲和力大于第一发射极层的电子亲和力,并且具有约3nm的厚度。
    • 3. 发明授权
    • Multilayer vertical transistor having an overlay electrode connected to
the top layer of the transistor and to the transistor substrate
    • 多层垂直晶体管具有连接到晶体管的顶层和晶体管衬底的覆盖电极
    • US5373185A
    • 1994-12-13
    • US121500
    • 1993-09-16
    • Hiroya Sato
    • Hiroya Sato
    • H01L29/205H01L21/331H01L27/06H01L27/082H01L29/73H01L29/737H01L29/70H01L29/52H01L29/54
    • H01L29/7371H01L27/0605H01L27/082
    • A vertical type construction transistor of this invention includes: a semiconductor substrate; a semiconductor multilayer formed on the semiconductor substrate, the semiconductor multilayer including at least an emitter layer, a collector layer, and a base layer; a first electrode electrically connected to the base layer; a second electrode electrically connected to one of the emitter layer and the collector layer; a third electrode formed on the semiconductor multilayer, and electrically connected to the other of the emitter layer and the collector layer, the third electrode being extended in a first direction; an insulating film formed substantially over the semiconductor multilayer; and an overlay electrode at least partially formed on the insulating film, the overlay electrode being electrically connected to the third electrode, at least partially formed on the insulating film, and extending out in a direction normal to the first direction so as to be in partial contact with the semiconductor substrate, the overlay electrode having a width substantially similar to the length of the third electrode in the first direction.
    • 本发明的垂直型结构晶体管包括:半导体衬底; 形成在所述半导体衬底上的所述半导体层,所述半导体层至少包括发射极层,集电极层和基极层; 电连接到所述基底层的第一电极; 电连接到发射极层和集电极层之一的第二电极; 形成在所述半导体多层上的第三电极,并且电连接到所述发射极层和所述集电极层中的另一个,所述第三电极沿第一方向延伸; 基本上形成在半导体多层上的绝缘膜; 以及至少部分地形成在所述绝缘膜上的覆盖电极,所述覆盖电极电连接到所述第三电极,至少部分地形成在所述绝缘膜上,并且沿着与所述第一方向正交的方向延伸以部分地 与半导体衬底接触,覆盖电极具有与第一方向上的第三电极的长度基本相似的宽度。
    • 4. 发明授权
    • Method of fabricating a semiconductor device
    • 制造半导体器件的方法
    • US5252500A
    • 1993-10-12
    • US843346
    • 1992-02-28
    • Hiroya Sato
    • Hiroya Sato
    • H01L29/205H01L21/28H01L21/331H01L29/73H01L29/737H01L21/265
    • H01L29/66318H01L21/28Y10S148/011Y10S148/072
    • There is provided a method of fabricating a semiconductor device. This method includes the steps of: forming a collector layer, a base layer, an emitter layer, and a dummy layer; patterning the dummy layer and the emitter layer into a mesa structure; forming a base electrode on the base layer in self-alignment to the mesa structure, and simultaneously forming a base electrode material on the dummy layer; forming a surface planarization film on the base layer to cover sides of the mesa structure; and removing the base electrode material and the dummy layer. The removal of the dummy layer is performed by subjecting the dummy layer to an etchant through an opening in the base electrode material.
    • 提供了制造半导体器件的方法。 该方法包括以下步骤:形成集电极层,基极层,发射极层和虚设层; 将所述虚设层和所述发射极层图案化成台面结构; 在基底层上形成与台面结构自对准的基极,同时在虚设层上形成基极材料; 在所述基底层上形成表面平坦化膜以覆盖所述台面结构的侧面; 以及去除所述基极材料和所述虚设层。 虚拟层的去除是通过使基底电极材料中的开口对虚设层进行蚀刻而进行的。