专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07886085B2 Removable memory device, phase synchronizing method, phase synchronizing program, medium recording the same, and host terminal 有权
标题翻译：可移动存储设备，相位同步方法，相位同步程序，介质记录和主机终端
公开(公告)号：US07886085B2
公开(公告)日：2011-02-08
申请号：US12295051
申请日：2007-02-20
申请人： Hiroshi Suenaga , Osamu Shibata , Noriaki Takeda , Toru Iwata , Takaharu Yoshida , Yoshiyuki Saito
发明人： Hiroshi Suenaga , Osamu Shibata , Noriaki Takeda , Toru Iwata , Takaharu Yoshida , Yoshiyuki Saito
IPC分类号： G06F13/00 , G06F3/00
CPC分类号： H04L7/10 , G06F1/12 , H04L7/0008 , H04L7/033 , H04L7/044 , H04L7/046
摘要： An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time. A removable memory device that transmits/receives data to and from a host terminal, which includes: a clock reception section that receives a transmission/reception clock, which is used for transmitting/receiving data between the host terminal and the removable memory device, from the host terminal; a phase synchronization pattern generation section that generates a phase synchronization pattern, which is for adjusting a phase of internal reception clock which the host terminal incorporates for receiving data from the removable memory device, based on the transmission/reception clock; and a transmission section that transmits the generated phase synchronization pattern to the host terminal, and in which the phase synchronization pattern includes a first level signal which lasts for at least two cycles, and a second level signal which follows the first level signal and lasts for one cycle, is provided.
摘要翻译：本发明的目的是提供一种提高数据传输效率的技术，其允许同时正确地接收数据。一种向主机终端发送/接收数据的可移动存储装置，包括：接收用于在主机终端和可移动存储装置之间发送/接收数据的发送/接收时钟的时钟接收部分，主机终端; 相位同步模式生成部，其基于所述发送接收时钟生成相位同步模式，所述相位同步模式用于调整所述主机终端结合的用于从所述可移动存储装置接收数据的内部接收时钟的相位; 以及发送部，其将所生成的相位同步模式发送到所述主机终端，并且所述相位同步模式包括持续至少两个周期的第一电平信号，以及在所述第一电平信号之后持续的第二电平信号，提供一个循环。

2. 发明申请

US20120021640A1 COMMUNICATION CABLE 审中-公开
标题翻译：通讯电缆
公开(公告)号：US20120021640A1
公开(公告)日：2012-01-26
申请号：US13257560
申请日：2010-04-26
申请人： Kohei Masuda , Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito
发明人： Kohei Masuda , Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito
IPC分类号： H01R11/00
CPC分类号： H04L25/0272
摘要： A serial-parallel conversion circuit provided on one end of a cable body converts a first serial signal into parallel signals and outputs the parallel signals to parallel signal lines. A parallel-serial conversion circuit provided on another end of the cable body converts the parallel signals inputted from the parallel signal lines into a second serial signal and outputs the second serial signal to outside.
摘要翻译：设置在电缆体的一端的串行并行转换电路将第一串行信号转换为并行信号，并将并行信号输出到并行信号线。在电缆体的另一端设置并行转换电路，将从并行信号线输入的并行信号变换为第二串行信号，并将第二串行信号输出到外部。

3. 发明授权

US07899960B2 Host device 有权
标题翻译：主机设备
公开(公告)号：US07899960B2
公开(公告)日：2011-03-01
申请号：US12402016
申请日：2009-03-11
申请人： Osamu Shibata , Hiroshi Suenaga , Yoshiyuki Saito
发明人： Osamu Shibata , Hiroshi Suenaga , Yoshiyuki Saito
IPC分类号： G06F13/12 , G06F13/38
CPC分类号： G06F13/1689
摘要： A card controller receives data from a recording card via a socket. A read clock is transmitted in a main transmission wiring, and the data is transmitted in a data transmission wiring. The read clock is withdrawn from the card controller by an outgoing transmission wiring and retrieved into the card controller by an incoming transmission wiring. A transmission delay amount of the outgoing transmission wiring is equal to that of the main transmission wiring, and a transmission delay amount of the incoming transmission wiring is equal to that of the data transmission wiring. The card controller receives the data in synchronization with the read clock retrieved by the incoming transmission wiring.
摘要翻译：卡控制器通过插座从记录卡接收数据。在主发送配线中发送读时钟，在数据发送配线中发送数据。读出时钟通过输出的传输线从卡控制器中取出，并通过输入的传输线被取回到卡控制器中。输出发送线路的发送延迟量与主发送配线的发送延迟量相同，输入发送配线的发送延迟量与数据发送配线的发送延迟量相同。卡控制器与由输入的传输线路检索的读取时钟同步地接收数据。

4. 发明申请

US20090233489A1 HOST DEVICE 有权
标题翻译：主机设备
公开(公告)号：US20090233489A1
公开(公告)日：2009-09-17
申请号：US12402016
申请日：2009-03-11
申请人： Osamu Shibata , Hiroshi Suenaga , Yoshiyuki Saito
发明人： Osamu Shibata , Hiroshi Suenaga , Yoshiyuki Saito
IPC分类号： H01R24/00
CPC分类号： G06F13/1689
摘要： A card controller receives data from a recording card via a socket. A read clock is transmitted in a main transmission wiring, and the data is transmitted in a data transmission wiring. The read clock is withdrawn from the card controller by an outgoing transmission wiring and retrieved into the card controller by an incoming transmission wiring. A transmission delay amount of the outgoing transmission wiring is equal to that of the main transmission wiring, and a transmission delay amount of the incoming transmission wiring is equal to that of the data transmission wiring. The card controller receives the data in synchronization with the read clock retrieved by the incoming transmission wiring.
摘要翻译：卡控制器通过插座从记录卡接收数据。在主发送配线中发送读时钟，在数据发送配线中发送数据。读出时钟通过输出的传输线从卡控制器中取出，并通过输入的传输线被取回到卡控制器中。输出发送线路的发送延迟量与主发送配线的发送延迟量相同，输入发送配线的发送延迟量与数据发送配线的发送延迟量相同。卡控制器与由输入的传输线路检索的读取时钟同步地接收数据。

5. 发明授权

US07385466B2 Differential transmission circuit and common mode choke coil 失效
标题翻译：差动传输电路和共模扼流线圈
公开(公告)号：US07385466B2
公开(公告)日：2008-06-10
申请号：US11085078
申请日：2005-03-22
申请人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito
发明人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito
IPC分类号： H03H7/00 , H04B3/28
CPC分类号： H01F17/06 , H01F2017/0093 , H01F2017/067 , H04L25/0272
摘要： A first transmission line for transmitting a first signal and a second transmission line for transmitting a second signal, which has the reverse phase of the first signal, are connected in series with a common mode choke coil. A third transmission line and fourth transmission line are each connected in series with the common mode choke coil, and transmit the first and second signals. A semiconductor device is connected in series with the third and fourth transmission lines, so as to transmit and receive the first and second signals. One end of a first terminator is connected in parallel with the first transmission line, and the other end is connected to the common mode choke coil. One end of a second terminator is connected in parallel with the second transmission line, and the other end is connected to the common mode choke coil. The noise eliminating capability of the common mode choke coil is increased by means of this structure.
摘要翻译：用于发送第一信号的第一传输线和用于发送具有第一信号的相反相位的第二信号的第二传输线与共模扼流线圈串联连接。第三传输线和第四传输线各自与共模扼流线圈串联连接，并发送第一和第二信号。半导体器件与第三和第四传输线串联连接，以便发送和接收第一和第二信号。第一终端器的一端与第一传输线并联连接，另一端连接到共模扼流线圈。第二终端器的一端与第二传输线并联连接，另一端连接到共模扼流线圈。通过这种结构，增加了共模扼流线圈的噪声消除能力。

6. 发明授权

US07843224B2 Interface circuit that can switch between single-ended transmission and differential transmission 有权
标题翻译：接口电路可以在单端传输和差分传输之间切换
公开(公告)号：US07843224B2
公开(公告)日：2010-11-30
申请号：US12262613
申请日：2008-10-31
申请人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito , Toru Iwata , Masayuki Toyama , Kyoko Hirata
发明人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito , Toru Iwata , Masayuki Toyama , Kyoko Hirata
IPC分类号： H03K19/094
CPC分类号： H04L25/028 , H04L25/0272
摘要： An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.
摘要翻译：本发明的目的是实现在两个传输系统之间切换的接口电路中的输出级驱动器的面积的减小。接口电路具有两个驱动电路和驱动控制电路，该电路可以在作为电压驱动系统和电流驱动系统的两个驱动系统之间切换。两个驱动电路通过驱动控制电路连接到电源电位。通过选择电路输入输入信号的两个输入信号和反相逻辑信号。根据输入到驱动控制电路的控制信号，接口电路在电压驱动型单端传输系统和电流驱动型差动传输系统之间切换。

7. 发明申请

US20090108872A1 INTERFACE CIRCUIT THAT CAN SWITCH BETWEEN SINGLE-ENDED TRANSMISSION AND DIFFERENTIAL TRANSMISSION 有权
标题翻译：可以在单端传输和差分传输之间切换的接口电路
公开(公告)号：US20090108872A1
公开(公告)日：2009-04-30
申请号：US12262613
申请日：2008-10-31
申请人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito , Toru Iwata , Masayuki Toyama , Kyoko Hirata
发明人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito , Toru Iwata , Masayuki Toyama , Kyoko Hirata
IPC分类号： H03K19/0175
CPC分类号： H04L25/028 , H04L25/0272
摘要： An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.
摘要翻译：本发明的目的是实现在两个传输系统之间切换的接口电路中的输出级驱动器的面积的减小。接口电路具有两个驱动电路和驱动控制电路，该电路可以在作为电压驱动系统和电流驱动系统的两个驱动系统之间切换。两个驱动电路通过驱动控制电路连接到电源电位。通过选择电路输入输入信号的两个输入信号和反相逻辑信号。根据输入到驱动控制电路的控制信号，接口电路在电压驱动型单端传输系统和电流驱动型差动传输系统之间切换。

8. 发明申请

US20060050820A1 Data transmission device and data transmission method 审中-公开
标题翻译：数据传输设备和数据传输方式
公开(公告)号：US20060050820A1
公开(公告)日：2006-03-09
申请号：US10539235
申请日：2004-02-10
申请人： Hirotsugu Kawada , Yoshiyuki Saito , Osamu Shibata , Hiroshi Suenaga , Takahisa Sakai , Toshitomo Umei , Takashi Akita , Yuji Mizuguchi , Noboru Katta
发明人： Hirotsugu Kawada , Yoshiyuki Saito , Osamu Shibata , Hiroshi Suenaga , Takahisa Sakai , Toshitomo Umei , Takashi Akita , Yuji Mizuguchi , Noboru Katta
IPC分类号： H04L7/00
CPC分类号： H04L7/00 , H04L7/0334
摘要： A signal receiver (11) receives an analog signal via a twisted pair cable (31). An A/D converter (12) converts the analog signal to a digital signal. A phase detection unit (14) detects the phase of the digital signal, and generates a reception timing signal. A transmission timing generation unit (15) controls, based on the reception timing signal, timing for a transmission processing unit (16) to output the digital signal such that the reception signal (point A) and a transmission signal (point D) are different in phase by a predetermined degree. The transmission processing unit (16) outputs, in accordance with the timing, a digital signal obtained by performing mapping on data inputted from a connection device (20). A D/A converter (17) converts the digital signal to an analog signal. A signal transmitter (18) transmits the analog signal via a twisted pair cable (32).
摘要翻译：信号接收器（11）经由双绞线电缆（31）接收模拟信号。 A / D转换器（12）将模拟信号转换成数字信号。相位检测单元（14）检测数字信号的相位，并产生接收定时信号。发送定时生成单元（15）基于接收定时信号，控制发送处理单元（16）输出数字信号的定时，使得接收信号（点A）和发送信号（点D）不同同时预定的程度。发送处理单元（16）根据定时输出通过对从连接装置（20）输入的数据进行映射而获得的数字信号。 D / A转换器（17）将数字信号转换成模拟信号。信号发送器（18）经由双绞线电缆（32）发送模拟信号。

9. 发明授权

US08548069B2 Data transmission system capable of transmitting interrupt signal without interrupt gate period 有权
标题翻译：数据传输系统能够在不中断门限周期的情况下传输中断信号
公开(公告)号：US08548069B2
公开(公告)日：2013-10-01
申请号：US13142655
申请日：2010-10-13
申请人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito , Kohei Masuda , Yoshihide Komatsu , Masashi Suzuki
发明人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito , Kohei Masuda , Yoshihide Komatsu , Masashi Suzuki
IPC分类号： H04B3/00
CPC分类号： H04L25/0278
摘要： A data transmission system comprises: a pair of transmission lines connecting a plurality of apparatuses; a bridge termination resistor connected between the transmission lines and having a resistance value matching a differential impedance of the transmission lines; a first switch connecting the bridge termination resistor to the transmission lines when being turned on, and disconnecting the bridge termination resistor from the transmission lines when being turned off; pull-up/down resistors connected between the transmission lines and a fixed voltage node, and having resistance values respectively matching characteristic impedances of the transmission lines, the fixed voltage node being a power supply or a ground; and second switches connecting the pull-up/down resistors between the transmission lines and the fixed voltage node when being turned on, and disconnecting the pull-up/down resistors from the transmission lines when being turned off.
摘要翻译：数据传输系统包括：一对连接多个设备的传输线; 连接在传输线之间并具有与传输线的差分阻抗匹配的电阻值的桥接终端电阻; 第一开关，其在接通时将桥接端接电阻器连接到传输线;以及当断开时将桥接终端电阻器与传输线路断开; 连接在传输线路和固定电压节点之间的上拉/下拉电阻器，具有分别匹配传输线路的特征阻抗，固定电压节点为电源或接地的电阻值; 以及第二开关，其在接通时将传输线和固定电压节点之间的上拉/下拉电阻连接起来，以及在断开时从传输线断开上拉/下拉电阻。

10. 发明申请

US20120112784A1 DIFFERENTIAL SIGNAL TRANSMISSION LINE, IC PACKAGE, AND METHOD FOR TESTING SAID DIFFERENTIAL SIGNAL TRANSMISSION LINE AND IC PACKAGE 审中-公开
标题翻译：差分信号传输线，IC封装和测试差分信号传输线和IC封装的方法
公开(公告)号：US20120112784A1
公开(公告)日：2012-05-10
申请号：US13383726
申请日：2011-04-13
申请人： Kohei Masuda , Osamu Shibata , Hiroshi Suenaga , Yoshiyuki Saito
发明人： Kohei Masuda , Osamu Shibata , Hiroshi Suenaga , Yoshiyuki Saito
IPC分类号： G01R31/26 , G01R31/02 , H01L23/48 , H01B11/00
CPC分类号： H04B3/30 , G01R31/002 , H01L22/32 , H01L23/66 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2223/6638 , H01L2224/48227 , H01L2224/48247 , H01L2224/49171 , H01L2924/00014 , H01L2924/14 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H04B3/46 , H04B3/50 , H04L25/0272 , H04L25/0276 , H04L25/0278 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An IC package includes an integrated circuit for transmitting and receiving a pair of differential signals composed of a signal having positive polarity and a signal having negative polarity, a first signal terminal for transmitting the signal having positive polarity, a second signal terminal for transmitting the signal having negative polarity, and a third terminal arranged between the first signal terminal and the second signal terminal. The first and second terminals are electrically connected to the integrated circuit, and the third terminal is not electrically connected to the integrated circuit.
摘要翻译： IC封装包括用于发送和接收由具有正极性的信号和具有负极性的信号组成的一对差分信号的集成电路，用于发送具有正极性的信号的第一信号端子，用于发送信号的第二信号端子具有负极性，第三端子布置在第一信号端子和第二信号端子之间。第一和第二端子电连接到集成电路，并且第三端子不与集成电路电连接。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式