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1. 发明授权

US07981750B2 Methods of fabrication of channel-stressed semiconductor devices 有权
标题翻译：通道应力半导体器件的制造方法
公开(公告)号：US07981750B2
公开(公告)日：2011-07-19
申请号：US12138502
申请日：2008-06-13
申请人： Hion-suck Baik , Jong-bong Park , Jung-yun Won , Hwa-sung Rhee , Byung-seo Kim , Ho Lee , Myung-sun Kim , Ji-hye Yi
发明人： Hion-suck Baik , Jong-bong Park , Jung-yun Won , Hwa-sung Rhee , Byung-seo Kim , Ho Lee , Myung-sun Kim , Ji-hye Yi
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： In one aspect, a method of fabricating a semiconductor device is provided. The method includes forming at least one capping layer over epitaxial source/drain regions of a PMOS device, forming a stress memorization (SM) layer over the PMOS device including the at least one capping layer and over an adjacent NMOS device, and treating the SM layer formed over the NMOS and PMOS devices to induce tensile stress in a channel region of the NMOS device.
摘要翻译：一方面，提供一种制造半导体器件的方法。该方法包括在PMOS器件的外延源极/漏极区域上形成至少一个覆盖层，在包括至少一个覆盖层并且在相邻的NMOS器件上的PMOS器件上形成应力记忆（SM）层，以及处理SM 形成在NMOS和PMOS器件上的层，以在NMOS器件的沟道区域中引起拉伸应力。

2. 发明申请

US20110073941A1 Semiconductor Devices Including Elevated Source and Drain Regions 有权
标题翻译：包括高压源和排水区的半导体器件
公开(公告)号：US20110073941A1
公开(公告)日：2011-03-31
申请号：US12962061
申请日：2010-12-07
申请人： Jin Bum Kim , Young-Pil Kim , Jung-Yun Won , Hion-Suck Baik , Jun-Ho Lee
发明人： Jin Bum Kim , Young-Pil Kim , Jung-Yun Won , Hion-Suck Baik , Jun-Ho Lee
IPC分类号： H01L27/088
CPC分类号： H01L21/823456 , H01L21/823418 , H01L27/1052 , H01L27/10876 , H01L27/10894 , H01L29/4236 , H01L29/66621
摘要： Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.
摘要翻译：提供制造半导体器件的方法。制备具有活性图案和隔离层图案的基板。每个隔离层图案的上表面高于每个活动图案的上表面。在基板上形成具有均匀厚度的间隔层。蚀刻间隔层以在每个隔离层图案的侧壁上形成间隔物。在每个有源图案上形成栅极结构。对具有栅极结构的有源图案进行选择性外延生长（SEG）处理，以在活性图案上形成具有高于绝缘层图案的上表面的隔离的外延层。还提供了相关的半导体器件。

3. 发明申请

US20080210922A1 Storage nodes and methods of manufacturing and operating the same, phase change memory devices and methods of manufacturing and operating the same 审中-公开
标题翻译：存储节点和制造和操作方法相同，相变存储器件及其制造和操作方法
公开(公告)号：US20080210922A1
公开(公告)日：2008-09-04
申请号：US12000829
申请日：2007-12-18
申请人： Jun-ho Lee , Sung-kwan Kang , Hion-suck Baik , Jong-wook Lee
发明人： Jun-ho Lee , Sung-kwan Kang , Hion-suck Baik , Jong-wook Lee
IPC分类号： H01L47/00 , H01L21/28 , G11C11/00
CPC分类号： H01L45/144 , G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1666
摘要： In various embodiments, the present disclosure may provide a storage node. In various implementations, the storage node may include a bottom electrode having a non-planar bottom surface that conforms with and is connected to a non-planar top surface of a diode electrode of a memory device. The storage node may further include a phase change layer on top of a bottom diode and a top electrode on a top surface of a phase change layer.
摘要翻译：在各种实施例中，本公开可以提供存储节点。在各种实施方式中，存储节点可以包括底部电极，其具有与存储器件的二极管电极的非平面顶表面一致并连接到非平面底表面的底部电极。存储节点还可以在底二极管的顶部和相变层的顶表面上的顶电极之间包括相变层。

4. 发明申请

US20070023810A1 Capacitor, semiconductor device having the same, and method of manufacturing the semiconductor device 审中-公开
标题翻译：具有相同的电容器，半导体器件以及半导体器件的制造方法
公开(公告)号：US20070023810A1
公开(公告)日：2007-02-01
申请号：US11529611
申请日：2006-09-29
申请人： Hion-suck Baik , Jung-hyun Lee , Jong-bong Park , Yun-chang Park
发明人： Hion-suck Baik , Jung-hyun Lee , Jong-bong Park , Yun-chang Park
IPC分类号： H01L29/94 , H01L27/108 , H01L29/00
CPC分类号： H01L28/75 , H01L21/28556 , H01L27/10852 , H01L27/10855 , H01L28/55 , H01L28/65 , H01L28/90 , H01L28/91
摘要： A semiconductor device with a stack type capacitor having a lower electrode formed of an aluminum-doped metal, and a manufacturing method thereof are provided. The semiconductor device includes: a semiconductor substrate having a gate structure and an active region; an interlayer dielectric film formed on the active region; a lower electrode formed of a metal containing aluminum on the interlayer dielectric film; a dielectric layer formed on the lower electrode; an upper electrode formed on the dielectric layer; and a plug formed in the interlayer dielectric film to electrically connect the active region with the lower electrode. The method includes: forming a gate structure and an active region on a semiconductor substrate; forming an interlayer dielectric film on the resultant semiconductor substrate; forming a plug in the interlayer dielectric film to electrically connect with the active region; forming a mold oxidation layer on the plug and the interlayer dielectric film; patterning the mold oxidation layer with a predetermined pattern and forming a lower electrode of material containing aluminum on the plug; and sequentially forming a dielectric layer and an upper electrode on the lower electrode.
摘要翻译：提供具有由铝掺杂金属形成的下电极的堆叠型电容器的半导体器件及其制造方法。半导体器件包括：具有栅极结构和有源区的半导体衬底; 形成在有源区上的层间绝缘膜; 在层间电介质膜上由含有铝的金属形成的下电极; 形成在下电极上的电介质层; 形成在电介质层上的上电极; 以及形成在所述层间电介质膜中以将所述有源区电连接到所述下电极的插塞。该方法包括：在半导体衬底上形成栅极结构和有源区; 在所得半导体衬底上形成层间绝缘膜; 在所述层间电介质膜中形成插塞以与所述有源区电连接; 在插塞和层间电介质膜上形成模具氧化层; 以预定图案图案化模具氧化层，并在插头上形成含有铝的材料的下电极; 并且在下电极上依次形成电介质层和上电极。

5. 发明授权

US08552494B2 Semiconductor devices including elevated source and drain regions 有权
标题翻译：半导体器件包括升高的源极和漏极区域
公开(公告)号：US08552494B2
公开(公告)日：2013-10-08
申请号：US12962061
申请日：2010-12-07
申请人： Jin-Bum Kim , Young-Pil Kim , Jung-Yun Won , Hion-Suck Baik , Jun-Ho Lee
发明人： Jin-Bum Kim , Young-Pil Kim , Jung-Yun Won , Hion-Suck Baik , Jun-Ho Lee
IPC分类号： H01L27/088
CPC分类号： H01L21/823456 , H01L21/823418 , H01L27/1052 , H01L27/10876 , H01L27/10894 , H01L29/4236 , H01L29/66621
摘要： Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.
摘要翻译：提供制造半导体器件的方法。制备具有活性图案和隔离层图案的基板。每个隔离层图案的上表面高于每个活动图案的上表面。在基板上形成具有均匀厚度的间隔层。蚀刻间隔层以在每个隔离层图案的侧壁上形成间隔物。在每个有源图案上形成栅极结构。对具有栅极结构的有源图案进行选择性外延生长（SEG）处理，以在活性图案上形成具有高于绝缘层图案的上表面的隔离的外延层。还提供了相关的半导体器件。

6. 发明授权

US07838422B2 Al-doped charge trap layer, non-volatile memory device and methods of fabricating the same 有权
标题翻译： Al掺杂电荷陷阱层，非易失性存储器件及其制造方法
公开(公告)号：US07838422B2
公开(公告)日：2010-11-23
申请号：US11892849
申请日：2007-08-28
申请人： Eun-ha Lee , Hion-suck Baik , Kwang-soo Seol , Sang-jin Park , Jong-bong Park , Min-ho Yang
发明人： Eun-ha Lee , Hion-suck Baik , Kwang-soo Seol , Sang-jin Park , Jong-bong Park , Min-ho Yang
IPC分类号： H01L21/44
CPC分类号： H01L29/42332 , Y10T428/259
摘要： Provided is an aluminum (Al) doped charge trap layer, a non-volatile memory device and methods of fabricating the same. The charge trap layer may include a plurality of silicon nano dots that trap charges and a silicon oxide layer that covers the silicon nano dots, wherein the charge trap layer is doped with aluminum (Al). The non-volatile memory device may include a substrate including a source and a drain on separate regions of the substrate, a tunneling film on the substrate contacting the source and the drain, the charge trap layer according to example embodiments, a blocking film on the charge trap layer, and a gate electrode on the blocking film.
摘要翻译：提供了铝（Al）掺杂的电荷阱层，非易失性存储器件及其制造方法。电荷陷阱层可以包括捕获电荷的多个硅纳米点和覆盖硅纳米点的氧化硅层，其中电荷陷阱层掺杂有铝（Al）。非挥发性存储器件可以包括衬底，该衬底包括在衬底的分离区域上的源极和漏极，在衬底上接触源极和漏极的隧道膜，根据示例性实施例的电荷陷阱层，电荷陷阱层和阻挡膜上的栅电极。

7. 发明申请

US20070152283A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070152283A1
公开(公告)日：2007-07-05
申请号：US11551994
申请日：2006-10-23
申请人： Hion-suck BAIK , Eun-ha LEE , Hyung-suk JUNG , Sung-kee HAN , Min-ho YANG
发明人： Hion-suck BAIK , Eun-ha LEE , Hyung-suk JUNG , Sung-kee HAN , Min-ho YANG
IPC分类号： H01L29/94 , H01L21/3205
CPC分类号： H01L21/28556 , H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device and a manufacturing method thereof for preventing gate electrode degradation and gate current leakage. The semiconductor device includes a gate insulating layer including an H-k (high dielectric) material on a semiconductor substrate, a barrier metal layer including a metal alloy on the gate insulating layer, and a gate electrode layer formed on the barrier metal layer. Illustratively, the barrier metal layer includes at least one of TaAlN (tantalum aluminum nitride) or TiAlN (titanium aluminum nitride). The barrier metal layer can include an oxidation-resistant material so that oxidation of the barrier metal layer is prevented during a subsequent annealing of the semiconductor device in an oxygen atmosphere. Thus, degradation of a gate electrode is prevented, and gate current leakage due to degradation of the gate electrode is prevented.
摘要翻译：一种用于防止栅电极劣化和栅极电流泄漏的半导体器件及其制造方法。半导体器件包括在半导体衬底上包括H-k（高电介质）材料的栅极绝缘层，在栅极绝缘层上包括金属合金的阻挡金属层和形成在阻挡金属层上的栅电极层。说明性地，阻挡金属层包括TaAlN（氮化钽）或TiAlN（氮化铝）中的至少一种。阻挡金属层可以包括抗氧化材料，从而在半导体器件在氧气氛中的随后的退火中防止了阻挡金属层的氧化。因此，防止了栅电极的劣化，并且防止了由于栅电极的劣化引起的栅极电流泄漏。

8. 发明申请

US20060244033A1 Capacitor, semiconductor device having the same, and method of manufacturing the semiconductor device 审中-公开
公开(公告)号：US20060244033A1
公开(公告)日：2006-11-02
申请号：US11475207
申请日：2006-06-27
申请人： Hion-suck Baik , Jung-hyun Lee , Jong-bong Park , Yun-chang Park
发明人： Hion-suck Baik , Jung-hyun Lee , Jong-bong Park , Yun-chang Park
IPC分类号： H01L29/94 , H01L27/108 , H01L29/00
CPC分类号： H01L28/75 , H01L21/28556 , H01L27/10852 , H01L27/10855 , H01L28/55 , H01L28/65 , H01L28/90 , H01L28/91
摘要： A semiconductor device with a stack type capacitor having a lower electrode formed of an aluminum-doped metal, and a manufacturing method thereof are provided. The semiconductor device includes: a semiconductor substrate having a gate structure and an active region; an interlayer dielectric film formed on the active region; a lower electrode formed of a metal containing aluminum on the interlayer dielectric film; a dielectric layer formed on the lower electrode; an upper electrode formed on the dielectric layer; and a plug formed in the interlayer dielectric film to electrically connect the active region with the lower electrode. The method includes: forming a gate structure and an active region on a semiconductor substrate; forming an interlayer dielectric film on the resultant semiconductor substrate; forming a plug in the interlayer dielectric film to electrically connect with the active region; forming a mold oxidation layer on the plug and the interlayer dielectric film; patterning the mold oxidation layer with a predetermined pattern and forming a lower electrode of material containing aluminum on the plug; and sequentially forming a dielectric layer and an upper electrode on the lower electrode.

9. 发明授权

US07875525B2 Method of manufacturing stack-type capacitor and semiconductor memory device having the stack-type capacitor 有权
标题翻译：具有堆叠型电容器的堆叠型电容器和半导体存储器件的制造方法
公开(公告)号：US07875525B2
公开(公告)日：2011-01-25
申请号：US12289966
申请日：2008-11-07
申请人： Jung-hyun Lee , Hion-suck Baik , Soon-ho Kim , Jae-young Choi
发明人： Jung-hyun Lee , Hion-suck Baik , Soon-ho Kim , Jae-young Choi
IPC分类号： H01L21/20
CPC分类号： H01L28/65 , H01L27/10852 , H01L28/75 , H01L28/91
摘要： A stack-type capacitor includes a lower electrode, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer, wherein the lower electrode includes a first metal layer having a cylindrical shape and a second metal layer filled in the first metal layer. In the capacitor, an amount of oxygen included in the lower electrode is decreased to suppress oxidation of a TiN layer. Thus, a stable stack-type capacitor may be formed, which increases greatly the performance of highly integrated DRAMs.
摘要翻译：堆叠型电容器包括下电极，形成在下电极上的电介质层和形成在电介质层上的上电极，其中下电极包括具有圆柱形状的第一金属层和填充在第二金属层中的第二金属层第一金属层。在电容器中，下部电极中包含的氧的量减少以抑制TiN层的氧化。因此，可以形成稳定的堆叠型电容器，这大大增加了高度集成的DRAM的性能。

10. 发明授权

US07867865B2 Methods of fabricating semiconductor devices including elevated source and drain regions 有权
标题翻译：制造包括升高的源极和漏极区域的半导体器件的方法
公开(公告)号：US07867865B2
公开(公告)日：2011-01-11
申请号：US12166575
申请日：2008-07-02
申请人： Jin-Bum Kim , Young-Pil Kim , Jung-Yun Won , Hion-Suck Baik , Jun-Ho Lee
发明人： Jin-Bum Kim , Young-Pil Kim , Jung-Yun Won , Hion-Suck Baik , Jun-Ho Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/823456 , H01L21/823418 , H01L27/1052 , H01L27/10876 , H01L27/10894 , H01L29/4236 , H01L29/66621
摘要： Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.
摘要翻译：提供制造半导体器件的方法。制备具有活性图案和隔离层图案的基板。每个隔离层图案的上表面高于每个活动图案的上表面。在基板上形成具有均匀厚度的间隔层。蚀刻间隔层以在每个隔离层图案的侧壁上形成间隔物。在每个有源图案上形成栅极结构。对具有栅极结构的有源图案进行选择性外延生长（SEG）处理，以在活性图案上形成具有高于绝缘层图案的上表面的隔离的外延层。还提供了相关的半导体器件。

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