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1. 再颁专利

USRE35978E Control circuit of dynamic random access memory 失效
标题翻译：动态随机存取存储器的控制电路
公开(公告)号：USRE35978E
公开(公告)日：1998-12-01
申请号：US660977
申请日：1996-06-12
申请人： Hidetada Fukunaka , Akira Ishiyama
发明人： Hidetada Fukunaka , Akira Ishiyama
IPC分类号： G11C11/409 , G11C7/10 , G11C7/22 , G11C8/18 , G11C7/00 , G11C8/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1078 , G11C8/18
摘要： A control circuit of a memory system including a dynamic random access memory may include a first integrated circuit formed on a common substrate. The first integrated circuit may include a circuit responsive to an external memory access request signal for generating a control signal for controlling an operation timing of the dynamic random access memory to supply the control signal to the dynamic random access memory and a circuit for generating an address signal for specifying an address of the dynamic random access memory to be accessed to supply the address signal to the dynamic random access memory. A second integrated circuit includes a read/write circuit for reading data from the dynamic random access memory and for writing data in the dynamic random access memory.
摘要翻译：包括动态随机存取存储器的存储器系统的控制电路可以包括形成在公共衬底上的第一集成电路。第一集成电路可以包括响应于外部存储器访问请求信号的电路，用于产生用于控制动态随机存取存储器的操作定时的控制信号，以将控制信号提供给动态随机存取存储器和用于产生地址的电路信号，用于指定要访问的动态随机存取存储器的地址以将地址信号提供给动态随机存取存储器。第二集成电路包括用于从动态随机存取存储器读取数据并用于在动态随机存取存储器中写入数据的读/写电路。

2. 发明授权

US5109382A Method and apparatus for testing a memory 失效
标题翻译：用于测试记忆的方法和装置
公开(公告)号：US5109382A
公开(公告)日：1992-04-28
申请号：US439838
申请日：1989-11-21
申请人： Hidetada Fukunaka
发明人： Hidetada Fukunaka
IPC分类号： G06F12/16 , G11C29/56
CPC分类号： G11C29/56
摘要： Method and apparatus for testing a memory mounted on an information processing system which includes a processor and at least one memory device. The memory device has a built-in memory test capability. In testing the memory mounted on the system, a test using the built-in test capability is combined with an additional test using a normal write/read operation of the memory performed by the processor unit. While the test using the built-in test capability is performed over the entire memory addresses, the additional test is performed with limited addresses.
摘要翻译：用于测试安装在信息处理系统上的存储器的方法和装置，其包括处理器和至少一个存储器件。内存设备具有内置的内存测试功能。在测试安装在系统上的内存时，使用内置测试功能的测试与使用处理器单元进行的存储器的正常写入/读取操作的附加测试相结合。虽然在整个存储器地址上执行使用内置测试功能的测试，但是使用有限的地址执行附加测试。

3. 发明授权

US06185481B2 Air cooled electronic equipment apparatus 失效
标题翻译：风冷电子设备设备
公开(公告)号：US06185481B2
公开(公告)日：2001-02-06
申请号：US08969361
申请日：1997-11-28
申请人： Yoshihiro Kondou , Tadakatsu Nakajima , Shigeo Ohashi , Susumu Iwai , Masayoshi Miyazaki , Shoohei Fuse , Kazuo Morita , Hidetada Fukunaka
发明人： Yoshihiro Kondou , Tadakatsu Nakajima , Shigeo Ohashi , Susumu Iwai , Masayoshi Miyazaki , Shoohei Fuse , Kazuo Morita , Hidetada Fukunaka
IPC分类号： G05B1300
CPC分类号： H05K7/20154 , H01L2924/0002 , H05K7/2019 , H01L2924/00
摘要： A semiconductor device provided with a first cooling fan and heat-radiating fins is mounted on a board, and there is provided a second cooling fan for supplying cooling air to the board, such that a flow passage is formed for directing the cooling air, supplied from the second cooling fan, toward the board through the first cooling fan.
摘要翻译：设置有第一冷却风扇和散热翅片的半导体装置安装在基板上，并且设置有用于向板供给冷却空气的第二冷却风扇，从而形成用于引导冷却空气的流动通道，供给从第二个冷却风扇，通过第一个冷却风扇朝向板子。

4. 发明授权

US5321666A Control circuit of dynamic random access memory 失效
标题翻译：动态随机存取存储器的控制电路
公开(公告)号：US5321666A
公开(公告)日：1994-06-14
申请号：US716821
申请日：1991-06-17
申请人： Hidetada Fukunaka , Akira Ishiyama
发明人： Hidetada Fukunaka , Akira Ishiyama
IPC分类号： G11C11/409 , G11C7/10 , G11C7/22 , G11C8/18 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1078 , G11C8/18
摘要： A control circuit of a memory system including a dynamic random access memory may include a first integrated circuit formed on a common substrate. The first integrated circuit may include a circuit responsive to an external memory access request signal for generating a control signal for controlling an operation timing of the dynamic random access memory to supply the control signal to the dynamic random access memory and a circuit for generating an address signal for specifying an address of the dynamic random access memory to be accessed to supply the address signal to the dynamic random access memory. A second integrated circuit includes a read/write circuit for reading data from the dynamic random access memory and for writing data in the dynamic random access memory.
摘要翻译：包括动态随机存取存储器的存储器系统的控制电路可以包括形成在公共衬底上的第一集成电路。第一集成电路可以包括响应于外部存储器访问请求信号的电路，用于产生用于控制动态随机存取存储器的操作定时的控制信号，以将控制信号提供给动态随机存取存储器和用于产生地址的电路信号，用于指定要访问的动态随机存取存储器的地址以将地址信号提供给动态随机存取存储器。第二集成电路包括用于从动态随机存取存储器读取数据并用于在动态随机存取存储器中写入数据的读/写电路。

5. 发明授权

US4779232A Partial write control apparatus 失效
标题翻译：部分写控制装置
公开(公告)号：US4779232A
公开(公告)日：1988-10-18
申请号：US52546
申请日：1987-05-20
申请人： Hidetada Fukunaka , Koichi Ikeda
发明人： Hidetada Fukunaka , Koichi Ikeda
IPC分类号： G06F12/04 , G11C7/00 , G11C7/10 , G11C11/40
CPC分类号： G11C7/1021
摘要： In a partial write control apparatus for a memory having a high speed operation mode such as a nibble mode or a page mode, when a partial write request for a plurality of words including those which require partial write is received, a memory control signal generator causes the memory to read successively all the words requiring partial write in a single high speed operation mode read cycle. A merging circuit merges those portions of the read-out words which need no alteration with write data and forms a group of updated complete words. Then, the memory control signal generator causes the memory to write successively these words in a single high speed operation mode write cycle.
摘要翻译：在具有诸如半字节模式或页面模式的高速操作模式的存储器的部分写入控制装置中，当接收到包括需要部分写入的多个字的多个字的部分写入请求时，存储器控制信号发生器导致存储器在单个高速操作模式读取周期中连续地读取所有需要部分写入的字。合并电路将不需要改变的读出单词的那些部分与写入数据相结合，并形成一组更新的完整单词。然后，存储器控制信号发生器使存储器以单个高速操作模式写入周期连续写入这些字。

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