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1. 发明授权

US08683181B2 Processor and method for distributing load among plural pipeline units 失效
标题翻译：用于在多个流水线单元之间分配负载的处理器和方法
公开(公告)号：US08683181B2
公开(公告)日：2014-03-25
申请号：US12926799
申请日：2010-12-09
申请人： Hideki Okawara
发明人： Hideki Okawara
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F9/3836 , G06F9/3861
摘要： An arithmetic processor includes a first pipeline unit configured to execute a first instruction that is input; a second pipeline unit configured to execute a second instruction that is input; a registration unit into which an aborted instruction is registered, the aborted instruction being the first instruction when the first pipeline unit is unable to complete the first instruction or the second instruction when the second pipeline unit is unable to complete the second instruction; a determination unit configured to make a determination as to which one of the first pipeline unit and the second pipeline unit is operating under a lower load; and an input unit configured to input, in the first pipeline unit or the second pipeline unit that is determined as operating under the lower load by the determination unit, the aborted instruction that is registered in the registration unit.
摘要翻译：算术处理器包括配置成执行被输入的第一指令的第一流水线单元; 配置为执行输入的第二指令的第二流水线单元; 注册单元，当所述第二流水线单元不能完成所述第二指令时，当所述第一流水线单元不能完成所述第一指令或所述第二指令时，所述中止指令是所述第一指令; 确定单元，被配置为对所述第一流水线单元和所述第二流水线单元中的哪个在较低的负载下进行操作; 以及输入单元，被配置为在所述第一流水线单元或所述第二流水线单元中，所述第一流水线单元或所述第二流水线单元通过所述确定单元在较低负载下操作，输入注册在所述注册单元中的中止的指令。

2. 发明申请

US20110161629A1 Arithmetic processor, information processor, and pipeline control method of arithmetic processor 失效
标题翻译：算术处理器，信息处理器和算术处理器的流水线控制方法
公开(公告)号：US20110161629A1
公开(公告)日：2011-06-30
申请号：US12926799
申请日：2010-12-09
申请人： Hideki Okawara
发明人： Hideki Okawara
IPC分类号： G06F9/302
CPC分类号： G06F9/3867 , G06F9/3836 , G06F9/3861
摘要： An arithmetic processor includes a first pipeline unit configured to execute a first instruction that is input; a second pipeline unit configured to execute a second instruction that is input; a registration unit into which an aborted instruction is registered, the aborted instruction being the first instruction when the first pipeline unit is unable to complete the first instruction or the second instruction when the second pipeline unit is unable to complete the second instruction; a determination unit configured to make a determination as to which one of the first pipeline unit and the second pipeline unit is operating under a lower load; and an input unit configured to input, in the first pipeline unit or the second pipeline unit that is determined as operating under the lower load by the determination unit, the aborted instruction that is registered in the registration unit.
摘要翻译：算术处理器包括配置成执行被输入的第一指令的第一流水线单元; 配置为执行输入的第二指令的第二流水线单元; 注册单元，当所述第二流水线单元不能完成所述第二指令时，当所述第一流水线单元不能完成所述第一指令或所述第二指令时，所述中止指令是所述第一指令; 确定单元，被配置为对所述第一流水线单元和所述第二流水线单元中的哪个在较低的负载下进行操作; 以及输入单元，被配置为在所述第一流水线单元或所述第二流水线单元中，所述第一流水线单元或所述第二流水线单元通过所述确定单元在较低负载下操作，输入注册在所述注册单元中的所述中止的指令。

3. 发明授权

US07954102B2 Scheduling method in multithreading processor, and multithreading processor 有权
标题翻译：多线程处理器和多线程处理器中的调度方法
公开(公告)号：US07954102B2
公开(公告)日：2011-05-31
申请号：US11122047
申请日：2005-05-05
申请人： Hideki Okawara
发明人： Hideki Okawara
IPC分类号： G06F9/46
CPC分类号： G06F9/4881
摘要： In regard to a scheduling method in a multithreading processor, a thread to be executed is dynamically selected from the threads allotted to the context units according to an operation state of the multithreading processor, and the number of threads to be executed simultaneously or the combination thereof is changed. Also, at the time of context switching, threads to be allotted to the context units are dynamically selected according to an operation state of the multithreading processor. As an example of a method for deciding the operation state, the decision is made by whether a set reference value is exceeded by the number of fetch stall times in a predetermined period on a thread-by-thread basis, number of missing cache times, memory access latency, IPC counter, or the like.
摘要翻译：关于多线程处理器中的调度方法，根据多线程处理器的操作状态和要同时执行的线程数或其组合，从被分配给上下文单元的线程动态地选择要执行的线程改变了此外，在上下文切换时，根据多线程处理器的操作状态来动态地选择要分配给上下文单元的线程。作为用于确定操作状态的方法的示例，通过在逐个线程的基础上超过预定时段内的获取失速时间的数量，设置的参考值是否丢失高速缓存时间的数量，内存访问延迟，IPC计数器等。

4. 发明授权

US08166250B2 Information processing unit, program, and instruction sequence generation method 失效
标题翻译：信息处理单元，程序和指令序列生成方法
公开(公告)号：US08166250B2
公开(公告)日：2012-04-24
申请号：US12334795
申请日：2008-12-15
申请人： Hideki Okawara , Masatoshi Haraguchi
发明人： Hideki Okawara , Masatoshi Haraguchi
IPC分类号： G06F12/08
CPC分类号： G06F9/383 , G06F9/3455
摘要： An information processing unit includes at least one cache memory provided between an instruction execution section and a storage section and a control section controlling content of address information based on a result of comparison processing between an address requested by a hardware prefetch request issuing section for memory access and address information held in an address information holding section, wherein when the control section causes the address information holding section to hold address information or address information in the address information holding section is updated, overwrite processing on the address information is inhibited for a predetermined time.
摘要翻译：信息处理单元包括：指令执行部和存储部之间提供的至少一个高速缓存存储器和控制部，其基于硬件预取请求发出部所请求的存储器访问的地址之间的比较处理结果来控制地址信息的内容以及保存在地址信息保持部分中的地址信息，其中当控制部分使地址信息保持部分保存地址信息或地址信息保存部分中的地址信息时，对地址信息的覆盖处理被禁止预定时间。

5. 发明申请

US20100095070A1 INFORMATION PROCESSING APPARATUS AND CACHE MEMORY CONTROL METHOD 失效
标题翻译：信息处理设备和高速缓存存储器控制方法
公开(公告)号：US20100095070A1
公开(公告)日：2010-04-15
申请号：US12639587
申请日：2009-12-16
申请人： HIDEKI OKAWARA , IWAO YAMAZAKI
发明人： HIDEKI OKAWARA , IWAO YAMAZAKI
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： An information processing apparatus including a main memory and a processor, the processor includes: a cache memory that stores data fetched to the cache memory; an instruction processing unit that accesses a part of the data in the cache memory sub block by sub block; an entry holding unit that holds a plurality of entries including a plurality of block addresses and access history information; and a controller that controls fetching of data from the main memory to the cache memory, while the access by the instruction processing unit to sub blocks of data in a block indicated by another of the entries immediately preceding the one of the entries, in accordance with order of the access from the instruction processing unit to sub blocks in the block indicated by the another of the entries and access history information associated with the one of the entries.
摘要翻译：一种包括主存储器和处理器的信息处理装置，所述处理器包括：高速缓存存储器，其将获取的数据存储到所述高速缓冲存储器中; 指令处理单元，其通过子块访问高速缓冲存储器子块中的一部分数据; 条目保持单元，保存包括多个块地址和访问历史信息的多个条目; 以及控制器，其控制从主存储器到高速缓冲存储器的数据取出，同时由指令处理单元访问由紧接在一个条目之前的另一个条目指示的块中的数据块，根据从指令处理单元到由另一个条目指示的块中的子块的访问顺序以及与该条目中的一个相关联的访问历史信息。

6. 发明申请

US20090240887A1 INFORMATION PROCESSING UNIT, PROGRAM, AND INSTRUCTION SEQUENCE GENERATION METHOD 失效
标题翻译：信息处理单元，程序和指令序列生成方法
公开(公告)号：US20090240887A1
公开(公告)日：2009-09-24
申请号：US12334795
申请日：2008-12-15
申请人： Hideki OKAWARA , Masatoshi Haraguchi
发明人： Hideki OKAWARA , Masatoshi Haraguchi
IPC分类号： G06F12/08
CPC分类号： G06F9/383 , G06F9/3455
摘要： An information processing unit includes at least one cache memory provided between an instruction execution section and a storage section and a control section controlling content of address information based on a result of comparison processing between an address requested by a hardware prefetch request issuing section for memory access and address information held in an address information holding section, wherein when the control section causes the address information holding section to hold address information or address information in the address information holding section is updated, overwrite processing on the address information is inhibited for a predetermined time.
摘要翻译：信息处理单元包括：指令执行部和存储部之间提供的至少一个高速缓存存储器和控制部，其基于硬件预取请求发出部所请求的存储器访问的地址之间的比较处理结果来控制地址信息的内容以及保存在地址信息保持部分中的地址信息，其中当控制部分使地址信息保持部分保存地址信息或地址信息保存部分中的地址信息时，对地址信息的覆盖处理被禁止预定时间。

7. 发明授权

US5508293A Pyridinecarboxyimidamide compounds and the use thereof 失效
标题翻译：吡啶甲脒类化合物及其用途
公开(公告)号：US5508293A
公开(公告)日：1996-04-16
申请号：US256625
申请日：1994-09-27
申请人： Hideki Okawara , Tatsuo Nakajima , Nobuyuki Ogawa , Tomoko Kashiwabara , Soichiro Kaneta
发明人： Hideki Okawara , Tatsuo Nakajima , Nobuyuki Ogawa , Tomoko Kashiwabara , Soichiro Kaneta
IPC分类号： A61K31/44 , C07D213/78 , C07D213/82
CPC分类号： C07D213/78
摘要： Disclosed are pyridinecarboximidamides having a vasodilating effect (hypotensive activity or antianginal activity), and acid adduct salts thereof. ##STR1## wherein when R.sup.1 represents an alkyl, hydroxyalkyl, carboxyl, amino, acylamino, alkylamino, dialkylamino, aralkylamino, alkylsulfonamide, bisalkylsulfonylamino or hydroxyl group, R.sup.2 represents a hydrogen atom and R.sup.3 represents a nitroxyl, 2-chlorophenyl or phenyl group; andwhen R.sup.1 represents a hydrogen atom, R.sup.2 represents an alkyl, hydroxyalkyl, carboxyl, amino, acylamino, alkylamino, dialkylamino, aralkylamino, alkylsulfonamide, bisalkylsulfonylamino or hydroxyl group and R.sup.3 represents a nitroxyl, 2-chlorophenyl or phenyl group.There is also disclosed the use of the compounds represented by the formula (I) for antihypertensive or antianginal purpose.
摘要翻译： PCT No.PCT / JP93 / 00103 Sec。 371日期：1994年9月27日 102（e）1994年9月27日PCT 1993年1月28日PCT公布。第WO93 / 15057号公报日期：1993年8月5日。公开的是具有血管扩张作用（降血压活性或抗血管活性）的吡啶甲脒和其酸加成盐。（I）其中当R 1表示烷基，羟烷基，羧基，氨基，酰氨基，烷基氨基，二烷基氨基，芳烷基氨基，烷基磺酰胺，双烷基磺酰基氨基或羟基时，R 2表示氢原子，R 3表示硝酰基，2-氯苯基或苯基组; 当R 1表示氢原子时，R 2表示烷基，羟烷基，羧基，氨基，酰氨基，烷基氨基，二烷基氨基，芳烷基氨基，烷基磺酰胺，双烷基磺酰基氨基或羟基，R 3表示硝酰基，2-氯苯基或苯基。还公开了由式（I）表示的化合物用于抗高血压或抗血管功能的用途。

8. 发明授权

US08225070B2 Information processing apparatus and cache memory control method 失效
标题翻译：信息处理装置和缓存存储器控制方法
公开(公告)号：US08225070B2
公开(公告)日：2012-07-17
申请号：US12639587
申请日：2009-12-16
申请人： Hideki Okawara , Iwao Yamazaki
发明人： Hideki Okawara , Iwao Yamazaki
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： An information processing apparatus including a main memory and a processor, the processor includes: a cache memory that stores data fetched to the cache memory; an instruction processing unit that accesses a part of the data in the cache memory sub block by sub block; an entry holding unit that holds a plurality of entries including a plurality of block addresses and access history information; and a controller that controls fetching of data from the main memory to the cache memory, while the access by the instruction processing unit to sub blocks of data in a block indicated by another of the entries immediately preceding the one of the entries, in accordance with order of the access from the instruction processing unit to sub blocks in the block indicated by the another of the entries and access history information associated with the one of the entries.
摘要翻译：一种包括主存储器和处理器的信息处理装置，所述处理器包括：高速缓存存储器，其将获取的数据存储到所述高速缓冲存储器中; 指令处理单元，其通过子块访问高速缓冲存储器子块中的一部分数据; 条目保持单元，保存包括多个块地址和访问历史信息的多个条目; 以及控制器，其控制从主存储器到高速缓冲存储器的数据取出，同时由指令处理单元访问由紧接在一个条目之前的另一个条目指示的块中的数据块，根据从指令处理单元到由另一个条目指示的块中的子块的访问顺序以及与该条目中的一个相关联的访问历史信息。

9. 发明申请

US20050210471A1 Scheduling method in multithreading processor, and multithreading processor 有权
标题翻译：多线程处理器和多线程处理器中的调度方法
公开(公告)号：US20050210471A1
公开(公告)日：2005-09-22
申请号：US11122047
申请日：2005-05-05
申请人： Hideki Okawara
发明人： Hideki Okawara
IPC分类号： G06F9/46 , G06F9/48
CPC分类号： G06F9/4881
摘要： In regard to a scheduling method in a multithreading processor, a thread to be executed is dynamically selected from the threads allotted to the context units according to an operation state of the multithreading processor, and the number of threads to be executed simultaneously or the combination thereof is changed. Also, at the time of context switching, threads to be allotted to the context units are dynamically selected according to an operation state of the multithreading processor. As an example of a method for deciding the operation state, the decision is made by whether a set reference value is exceeded by the number of fetch stall times in a predetermined period on a thread-by-thread basis, number of missing cache times, memory access latency, IPC counter, or the like.
摘要翻译：关于多线程处理器中的调度方法，根据多线程处理器的操作状态和要同时执行的线程数或其组合，从被分配给上下文单元的线程动态地选择要执行的线程改变了此外，在上下文切换时，根据多线程处理器的操作状态来动态地选择要分配给上下文单元的线程。作为用于确定操作状态的方法的示例，通过在逐个线程的基础上超过预定时段内的获取失速时间的数量，设置的参考值是否丢失高速缓存时间的数量，内存访问延迟，IPC计数器等。

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