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    • 1. 发明授权
    • Low overhead context intializations for arithmetic video codecs
    • 算术视频编解码器的低开销上下文初始化
    • US07463781B2
    • 2008-12-09
    • US10824152
    • 2004-04-14
    • Eric C. PearsonHarminder S. Banwait
    • Eric C. PearsonHarminder S. Banwait
    • G06K9/36G06K9/46H04N7/12H04N11/02H04B1/66
    • H04N19/42H04N19/91
    • A method for controlling an arithmetic codec context is disclosed. The method may include the steps of (A) reading a current value indicating one of a first condition and a second condition corresponding to a current context of a plurality of predetermined contexts, (B) generating an input state matching (i) an initial state in response to the first condition and (ii) an output state in response to the second condition, wherein the initial state has a predetermined value and the output state has a value generated by the method before receiving the current context and (C) generating a current output state by performing an arithmetic code operation on an input signal using the input state.
    • 公开了一种用于控制算术编解码器上下文的方法。 该方法可以包括以下步骤:(A)读取指示与多个预定上下文的当前上下文相对应的第一条件和第二条件之一的当前值,(B)生成输入状态匹配(i)初始状态 响应于第一条件和(ii)响应于第二条件的输出状态,其中初始状态具有预定值,并且输出状态具有在接收当前上下文之前通过该方法生成的值,以及(C)生成 通过使用输入状态对输入信号执行算术代码运算来确定电流输出状态。
    • 4. 发明授权
    • Method and/or apparatus for transcoding between H.264 CABAC and CAVLC entropy coding modes
    • 用于在H.264 CABAC和CAVLC熵编码模式之间进行代码转换的方法和/或装置
    • US07061410B1
    • 2006-06-13
    • US11183580
    • 2005-07-18
    • Eric C. PearsonHarminder S. Banwait
    • Eric C. PearsonHarminder S. Banwait
    • H03M7/00
    • H04N19/40
    • An apparatus comprising a first circuit, a second circuit and an output circuit. The first circuit may be configured to generate (i) one of a first set of entropy coded input signals or a second set of entropy coded input signals and (ii) a data path signal. The second circuit may be configured to generate (i) a first set of entropy encoded output signals in response to decoding the second set of entropy coded input signals, or (ii) a second set of entropy coded output signals in response to decoding the first set of entropy coded input signals. The second circuit may provide real time decoding and encoding on a macroblock basis. The output circuit may be configured to present an output signal in response to (i) one of the first set of entropy coded output signals or the second set of entropy coded output signals and (ii) the data path signal.
    • 一种包括第一电路,第二电路和输出电路的装置。 第一电路可以被配置为产生(i)第一组熵编码输入信号或第二组熵编码输入信号中的一个,以及(ii)数据路径信号。 第二电路可以被配置为响应于解码第二组熵编码的输入信号而产生(i)第一组熵编码的输出信号,或者(ii)第二组熵编码的输出信号,以响应于第一 一组熵编码输入信号。 第二电路可以在宏块的基础上提供实时解码和编码。 输出电路可以被配置为响应于(i)第一组熵编码输出信号或第二组熵编码的输出信号之一和(ii)数据路径信号而呈现输出信号。