专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07176758B2 Multi-stage output buffer 有权
标题翻译：多级输出缓冲器
公开(公告)号：US07176758B2
公开(公告)日：2007-02-13
申请号：US10934164
申请日：2004-09-03
申请人： Hans-Martin Rein , Hao Li
发明人： Hans-Martin Rein , Hao Li
IPC分类号： H03F3/45
CPC分类号： H03F1/0205 , H03B5/1209 , H03B5/1228 , H03B5/124 , H03F3/191 , H03F3/195 , H03F3/4508 , H03F3/50 , H03F2203/45704 , H03F2203/45706 , H03L7/099
摘要： A multi-stage output buffer is disclosed. The output buffer includes an emitter follower circuit coupled to a differential input that is configured to provide a substantially high input impedance at an input thereof, and provide a substantially low output impedance at an output thereof. An emitter coupled pair circuit is coupled to the output of the emitter follower circuit, and is configured to amplify the signal and further isolate an input circuit. The buffer further includes a base-grounded configuration transistor circuit coupled to an output of the emitter coupled pair circuit and having an output coupled to the differential output of the multi-stage output buffer. The base-grounded transistor circuit reduces a load impedance at the output of the emitter coupled pair circuit, improves decoupling of the external load from an input circuit when coupled thereto, and increases the output power.
摘要翻译：公开了一种多级输出缓冲器。输出缓冲器包括耦合到差分输入的射极跟随器电路，其被配置为在其输入处提供基本上高的输入阻抗，并且在其输出处提供基本上低的输出阻抗。发射极耦合对电路耦合到射极跟随器电路的输出，并被配置为放大信号并进一步隔离输入电路。缓冲器还包括耦合到发射极耦合对电路的输出并具有耦合到多级输出缓冲器的差分输出的输出的基极接地配置晶体管电路。基极接地晶体管电路降低了发射极耦合对电路输出端的负载阻抗，改善了外部负载与输入电路耦合时的去耦耦合，并提高了输出功率。

2. 发明申请

US20060049881A1 Output buffer with inductive voltage divider 有权
公开(公告)号：US20060049881A1
公开(公告)日：2006-03-09
申请号：US10934979
申请日：2004-09-03
申请人： Hans-Martin Rein , Hao Li
发明人： Hans-Martin Rein , Hao Li
IPC分类号： H03B1/00
CPC分类号： H03B5/1847 , H03F3/4508 , H03F2203/45554
摘要： An output buffer is disclosed and includes a differential output buffer input configured for coupling to a differential output of an input circuit. The output buffer further includes an inductive voltage divider circuit coupled to the differential output buffer input, and configured to weaken a loading at the differential output of the input circuit.

3. 发明授权

US07053722B2 Voltage controlled oscillator (VCO) with output buffer 有权
标题翻译：具有输出缓冲器的压控振荡器（VCO）
公开(公告)号：US07053722B2
公开(公告)日：2006-05-30
申请号：US10934168
申请日：2004-09-03
申请人： Hans-Martin Rein , Hao Li
发明人： Hans-Martin Rein , Hao Li
IPC分类号： H03B5/12
CPC分类号： H03B5/1847
摘要： An oscillator system is disclosed and includes an oscillator circuit having a differential output producing a differential output signal thereat having a frequency that is a function of an input voltage. The oscillator system further includes an output buffer coupled to the differential output of the oscillator circuit. The output buffer includes an inductive voltage divider circuit configured to weaken a loading at the oscillator differential output and it increases the output power.
摘要翻译：公开了一种振荡器系统，并且包括具有差分输出的振荡器电路，其产生具有作为输入电压的函数的频率的差分输出信号。振荡器系统还包括耦合到振荡器电路的差分输出的输出缓冲器。输出缓冲器包括一个电感分压器电路，配置为减弱振荡器差分输出的负载，并增加输出功率。

4. 发明授权

US4695940A Dynamic frequency divider with a mixer stage and an amplifier 失效
标题翻译：具有混频器级和放大器的动态分频器
公开(公告)号：US4695940A
公开(公告)日：1987-09-22
申请号：US835988
申请日：1986-03-04
申请人： Hans-Martin Rein
发明人： Hans-Martin Rein
IPC分类号： H03B19/00 , H03B19/14 , H03B21/02 , H03F3/45 , H02M5/00
CPC分类号： H03F3/45089 , H03B21/02 , H03F2203/45311 , H03F2203/45318 , H03F2203/45652 , H03F2203/45696 , H03F2203/45702
摘要： A dynamic frequency divider including a mixer stage and a transimpedance amplifier connected to the output of the mixer stage.
摘要翻译：一种动态分频器，包括混频器级和跨阻抗放大器，连接到混频器的输出端。

5. 发明授权

US4630046A Broadband switching network in matrix form 失效
标题翻译：宽带交换网络采用矩阵形式
公开(公告)号：US4630046A
公开(公告)日：1986-12-16
申请号：US688161
申请日：1984-12-31
申请人： Hans-Martin Rein
发明人： Hans-Martin Rein
IPC分类号： H03K17/62 , H04Q3/52 , H04Q9/00 , H04J3/02
CPC分类号： H03K17/6221 , H04Q3/521
摘要： A broadband switching network in matrix form composed of a plurality of rows and a plurality of columns, and including a plurality of crosspoint switching circuits each having an input and an output and each associated with a respective row and a respective column; a plurality of input circuits each associated with a respective row and connected to the input of each switching circuit associated with the respective row; and a plurality of output circuits each associated with a respective column and connected to the output of each switching circuit associated with the respective column. Each crosspoint switching circuit includes a transistor connected in common emitter configuration and control elements connected for applying to the emitter of the transistor a potential controlling the switching state of the crosspoint switching circuit and each input circuit and output circuit is a decoupling circuit. The network further includes a plurality of load resistors each associated with a respective column and each connected to that output circuit which is associated with the respective column, and a plurality of self-blocking stages each including a transistor connected in common base configuration and each connected in series between the output of at least one switching circuit and that load resistor which is associated with the same column as the at least one switching circuit.
摘要翻译：一种矩阵形式的宽带交换网络，由多行和多列组成，并且包括多个交叉点交换电路，每个交叉点交换电路具有输入和输出，并且各自与相应行和相应的列相关联; 多个输入电路，各自与相应行相关联并连接到与相应行相关联的每个开关电路的输入; 以及多个输出电路，每个输出电路各自与各个列相关联并连接到与相应列相关联的每个开关电路的输出。每个交叉点开关电路包括以共同发射极配置连接的晶体管和连接用于施加到晶体管的发射极的控制元件，控制交叉点开关电路的开关状态的电位，并且每个输入电路和输出电路是去耦电路。网络还包括多个负载电阻器，每个负载电阻器与相应的列相关联并且各自连接到与各个列相关联的该输出电路，以及多个自阻塞级，每个包括以共同的基本配置连接的晶体管，串联在至少一个开关电路的输出和与至少一个开关电路相同的列之间的负载电阻之间。

6. 发明授权

US07135936B2 Output buffer with inductive voltage divider 有权
标题翻译：带感性分压器的输出缓冲器
公开(公告)号：US07135936B2
公开(公告)日：2006-11-14
申请号：US10934979
申请日：2004-09-03
申请人： Hans-Martin Rein , Hao Li
发明人： Hans-Martin Rein , Hao Li
IPC分类号： H03B1/00
CPC分类号： H03B5/1847 , H03F3/4508 , H03F2203/45554
摘要： An output buffer is disclosed and includes a differential output buffer input configured for coupling to a differential output of an input circuit. The output buffer further includes an inductive voltage divider circuit coupled to the differential output buffer input, and configured to weaken a loading at the differential output of the input circuit.
摘要翻译：公开了输出缓冲器，并且包括被配置为耦合到输入电路的差分输出的差分输出缓冲器输入。输出缓冲器还包括耦合到差分输出缓冲器输入的电感分压器电路，并且被配置为削弱输入电路的差分输出端的负载。

7. 发明申请

US20060049880A1 VOLTAGE CONTROLLED OSCILLATOR (VCO) WITH OUTPUT BUFFER 有权
标题翻译：具有输出缓冲器的电压控制振荡器（VCO）
公开(公告)号：US20060049880A1
公开(公告)日：2006-03-09
申请号：US10934168
申请日：2004-09-03
申请人： Hans-Martin Rein , Hao Li
发明人： Hans-Martin Rein , Hao Li
IPC分类号： H03B1/00
CPC分类号： H03B5/1847
摘要： An oscillator system is disclosed and includes an oscillator circuit having a differential output producing a differential output signal thereat having a frequency that is a function of an input voltage. The oscillator system further includes an output buffer coupled to the differential output of the oscillator circuit. The output buffer includes an inductive voltage divider circuit configured to weaken a loading at the oscillator differential output and it increases the output power.
摘要翻译：公开了一种振荡器系统，并且包括具有差分输出的振荡器电路，其产生具有作为输入电压的函数的频率的差分输出信号。振荡器系统还包括耦合到振荡器电路的差分输出的输出缓冲器。输出缓冲器包括一个电感分压器电路，配置为减弱振荡器差分输出的负载，并增加输出功率。

8. 发明申请

US20060049871A1 Multi-stage output buffer 有权
标题翻译：多级输出缓冲器
公开(公告)号：US20060049871A1
公开(公告)日：2006-03-09
申请号：US10934164
申请日：2004-09-03
申请人： Hans-Martin Rein , Hao Li
发明人： Hans-Martin Rein , Hao Li
IPC分类号： H03F3/45
CPC分类号： H03F1/0205 , H03B5/1209 , H03B5/1228 , H03B5/124 , H03F3/191 , H03F3/195 , H03F3/4508 , H03F3/50 , H03F2203/45704 , H03F2203/45706 , H03L7/099
摘要： A multi-stage output buffer is disclosed having a differential input and a differential output. The output buffer includes an emitter follower circuit coupled to the differential input that is configured to provide a substantially high input impedance at an input thereof, and provide a substantially low output impedance at an output thereof. An emitter coupled pair circuit is coupled to the output of the emitter follower circuit, and is configured to amplify the signal and further isolate an input circuit when coupled to the differential input of the multi-stage output buffer from an external load when coupled to the differential output thereof. The buffer further includes a base-grounded transistor circuit coupled to an output of the emitter coupled pair circuit and having an output coupled to the differential output of the multi-stage output buffer. The base-grounded transistor circuit is configured to reduce a load impedance at the output of the emitter coupled pair circuit, thereby improving a speed thereof. The base-grounded transistor circuit further improves decoupling of the external load from an input circuit when coupled thereto and increases the output power.
摘要翻译：公开了具有差分输入和差分输出的多级输出缓冲器。输出缓冲器包括耦合到差分输入的射极跟随器电路，其被配置为在其输入处提供基本上高的输入阻抗，并且在其输出处提供基本上低的输出阻抗。发射极耦合对电路耦合到射极跟随器电路的输出端，并且被配置为放大信号并进一步隔离输入电路，当耦合到与多级输出缓冲器的差分输入耦合到多级输出缓冲器差分输出。缓冲器还包括耦合到发射极耦合对电路的输出的基极接地晶体管电路，并且具有耦合到多级输出缓冲器的差分输出的输出。基极接地晶体管电路被配置为减小发射极耦合对电路的输出处的负载阻抗，从而提高其速度。基极接地晶体管电路进一步改善外部负载与输入电路耦合时的去耦耦合，并提高输出功率。

9. 发明授权

US5391933A Driver circuit for generating pulses 失效
标题翻译：用于产生脉冲的驱动电路
公开(公告)号：US5391933A
公开(公告)日：1995-02-21
申请号：US958703
申请日：1992-10-09
申请人： Hans-Martin Rein
发明人： Hans-Martin Rein
IPC分类号： H01S3/00 , H03F3/45 , H03K5/02 , H03K5/08 , H04L25/02 , H04B10/04
CPC分类号： H03F3/45479 , H03K5/02
摘要： A driver circuit for producing pulses has first and second, sequentially connected differential amplifier stages and first and second adjustable offset voltage sources. The first offset voltage source is connected to an input of the first differential amplifier stage so that the pulse-duty ratio of a differential signal generated by the first differential amplifier stage is variable by adjusting the first offset voltage. The second offset voltage source is connected to an input of the second differential amplifier stage so that the turn-on voltage of a first transistor in the second differential amplifier stage, which is connected to an output of the driver circuit, can be made smaller by adjustment of the second offset voltage, which simultaneously results in an increase in the turn-off voltage for that transistor. The driver circuit is particularly suited for operating laser diodes in optical transmission systems and for pulse generators in measurement equipment.
摘要翻译：用于产生脉冲的驱动电路具有第一和第二顺序连接的差分放大器级和第一和第二可调偏移电压源。第一偏移电压源连接到第一差分放大器级的输入，使得由第一差分放大器级产生的差分信号的脉冲占空比可以通过调整第一偏移电压而变化。第二偏移电压源连接到第二差分放大器级的输入，使得连接到驱动器电路的输出的第二差分放大器级中的第一晶体管的导通电压可以由调整第二偏移电压，这同时导致该晶体管的截止电压的增加。驱动电路特别适用于在光传输系统和测量设备中的脉冲发生器上操作激光二极管。

10. 发明授权

US5015872A Method and circuit arrangement for generating a phase shifted clock pulse signal 失效
标题翻译：用于产生相移时钟脉冲信号的方法和电路装置
公开(公告)号：US5015872A
公开(公告)日：1991-05-14
申请号：US375686
申请日：1989-07-05
申请人： Hans-Martin Rein
发明人： Hans-Martin Rein
IPC分类号： H03K5/00 , H03K5/13 , H03K5/135 , H04J3/04 , H04J3/06
CPC分类号： H04J3/047 , H03K5/13 , H03K5/135 , H03K2005/00176 , H03K2005/00182 , H03K2005/00228 , H04J3/0685
摘要： A method and apparatus of generating a clock pulse signal, which is shifted by any desired, settable phase value between 0 and -.pi. by using two conventional phase shifters which can be set continuously between 0 and -.pi./2, wherein the two input ports of the first phase shifter are fed with the non-delayed frequency-halved signal and with the frequency-halved signal shifted in phase by -.pi./2, respectively, and the two input ports of the second phase shifter are fed with the frequency-halved signal shifted in phase by -.pi./2 and -.pi., respectively. Both phase shifters are actuated jointly, and subsequently the frequency of the thus phase shifted output signals being doubled again. The output or input signals or both of them of the two controllable phase shifters are each filtered through lowpass filters in such a manner that possibly existing harmonics are attenuated in amplitude relative to the frequency-halved signal whereby dynamic behavior and frequency behavior are improved considerably.
摘要翻译：一种产生时钟脉冲信号的方法和装置，其通过使用可以在0和-π/ 2之间连续设置的两个常规移相器在0和-pi之间移动任何期望的可设置相位值，其中两个输入端口第一移相器的第二移相器的两个输入端分别被馈送有非延迟的减频信号，并且分频信号被相位移位-π/ 2，并且第二移相器的两个输入端口被馈送到频率 - 减号信号分别以-pi / 2和-pi移相。两个移相器被联合地驱动，随后这样相移的输出信号的频率再次被倍增。两个可控移相器的输出或输入信号或两者均通过低通滤波器以这样一种方式进行滤波，使得可能存在的谐波相对于频率减半的信号在幅度上衰减，由此动态特性和频率特性得到显着改善。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式