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1. 发明授权

US4816115A Process of making via holes in a double-layer insulation 失效
标题翻译：在双层绝缘中制作通孔的工艺
公开(公告)号：US4816115A
公开(公告)日：1989-03-28
申请号：US172738
申请日：1988-03-23
申请人： Eva Horner , Reinhold Muhl , Hans-Joachim Trumpp
发明人： Eva Horner , Reinhold Muhl , Hans-Joachim Trumpp
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/3213 , H01L21/768 , B44C1/22 , B29C37/00 , C03C15/00 , C03C25/06
CPC分类号： H01L21/31138 , H01L21/76804
摘要： A method of making via holes in a double-layer insulation of nitride and polyimide. The via holes are made with one photomask only by applying a photoresist process with double exposure, and a multi-step dry etching process. The double exposure, which includes an image-wise exposure followed by blanket irradiation, achieves an edge angle in the photoresist between approx. 60.degree. and 70.degree., depending on the exposure time ratios. This angle is transferred into the polyimide layer in a dry etching process. In a first etching step with CF.sub.4 as etching gas the greater part of the polyimide is removed. For removing the residual polyimide in the via holes there now follows an etching step in O.sub.2. Etch bias is thus kept on a very low level. The nitride layer is then etched with CF.sub.4 as etching gas, with the etching process being executed in two steps, each followed by an etching step in O.sub.2 for laterally shifting the photoresist and the polyimide via the resist angle. By softening the step height a softer profile of the via holes is ensured, which permits very good covering by a second layer of metallurgy.
摘要翻译：在氮化物和聚酰亚胺的双层绝缘中制造通孔的方法。通孔仅通过使用双曝光的光致抗蚀剂工艺和多步骤干蚀刻工艺由一个光掩模制成。包括曝光后进行成像曝光的双重曝光在光致抗蚀剂中达到约 60°和70°，取决于曝光时间比。该干燥蚀刻工艺将该角度转移到聚酰亚胺层中。在用CF 4作为蚀刻气体的第一蚀刻步骤中，去除了大部分聚酰亚胺。为了去除通孔中的残余聚酰亚胺，现在在O 2中进行蚀刻步骤。因此，蚀刻偏压保持在非常低的水平。然后用CF4作为蚀刻气体蚀刻氮化物层，蚀刻过程分两步进行，随后在O 2中进行蚀刻步骤，以通过抗蚀剂角横向移动光致抗蚀剂和聚酰亚胺。通过软化台阶高度，确保通孔的较软的轮廓，这允许通过第二层冶金进行非常好的覆盖。

2. 发明授权

US5109267A Method for producing an integrated circuit structure with a dense multilayer metallization pattern 失效
标题翻译：一种具有致密多层金属化图案的集成电路结构的制造方法
公开(公告)号：US5109267A
公开(公告)日：1992-04-28
申请号：US731695
申请日：1991-07-17
申请人： Otto Koblinger , Hans-Joachim Trumpp
发明人： Otto Koblinger , Hans-Joachim Trumpp
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/522
CPC分类号： H01L21/7688 , H01L21/76801 , H01L21/76816 , H01L23/5226 , H01L2924/0002
摘要： Disclosed is a method for manufacturing a high-denisty multilayer metallization pattern on an integrated circuit structure. Also disclosed are integrated circuit structures made with such method. The components of the integrated circuit may be formed on the substrate using conventional processes. A first metallization pattern is then formed on the semiconductor substrate having at least one integrated circuit. Next, the first layer of a double-layer insulation is applied over the first metallization pattern, and a photoresist layer is applied over the first layer for planarizing the topology of the metallization pattern and for defining a pad mask by a photoprocess over a conductive pad. For planarization of the topology, the photoresist layer and the first layer of the double-layer insulation are reactive ion etched at substantially the same rate to a desired depth. This reactive ion etching step also removes the first layer of the double-layer insulation from the pad mask area thereby exposing a metal pad. On top of the planarized topology, the second layer of the double-layer insulation is applied, and vias are opened in the layer by a plurality of dry-etching steps. The second metalliation pattern is formed on this second layer. Then, another double-layer insulation is applied on top of the second metallization pattern, the first layer being an inorganic and the second layer an organic layer. After opening vias in the layers of this double-layer insulation by contour-etching, a third metallization pattern is applied. Optionally, a fourth metallization pattern can be formed on the integrated circuit structure.
摘要翻译：公开了一种在集成电路结构上制造高密度多层金属化图案的方法。还公开了使用这种方法制成的集成电路结构。可以使用常规工艺在基板上形成集成电路的部件。然后在具有至少一个集成电路的半导体衬底上形成第一金属化图案。接下来，在第一金属化图案上施加双层绝缘的第一层，并且在第一层上施加光致抗蚀剂层，以平坦化金属化图案的拓扑结构，并通过导电焊盘上的光刻工艺来限定焊盘掩模。为了平坦化拓扑，光致抗蚀剂层和双层绝缘体的第一层以基本上相同的速率对所需的深度进行反应离子蚀刻。该反应离子蚀刻步骤还从焊盘掩模区域去除第二层双层绝缘层，从而露出金属焊盘。在平坦化拓扑的顶部，施加双层绝缘层的第二层，并且通过多个干蚀刻步骤在该层中开通通路。在该第二层上形成第二金属化图案。然后，在第二金属化图案的顶部上施加另一双层绝缘体，第一层是无机物，第二层是有机层。在通过轮廓蚀刻在该双层绝缘层的层中打开通孔之后，施加第三金属化图案。可选地，可以在集成电路结构上形成第四金属化图案。

3. 发明授权

US4869781A Method for fabricating a semiconductor integrated circuit structure having a submicrometer length device element 失效
标题翻译：一种具有亚微米长度器件元件的半导体集成电路结构的制造方法
公开(公告)号：US4869781A
公开(公告)日：1989-09-26
申请号：US259082
申请日：1988-10-17
申请人： Wolfgang Euen , Dieter Hagmann , Hans-Joachim Trumpp
发明人： Wolfgang Euen , Dieter Hagmann , Hans-Joachim Trumpp
IPC分类号： H01L29/78 , H01L21/033 , H01L21/311 , H01L21/321 , H01L21/3213 , H01L21/336
CPC分类号： H01L29/66575 , H01L21/0337 , H01L21/31144 , H01L21/32105 , H01L21/32137 , Y10S257/90 , Y10S438/947 , Y10S438/95
摘要： A method for fabricating a semiconductor integrated circuit structure having a submicrometer length device element is described wherein a surface isolation pattern is formed in a semiconductor substrate to define regions which are designated to contain devices. A first insulating compound layer is formed on the surface of the semiconductor substrate which is designated to be in part the gate dielectric. Subsequently, a polycrystalline silicon layer is deposited onto the compound layer. The polycrystalline silicon layer is heavily doped by phosphorus ion implantation and annealed below about 850.degree. C. Polycrystalline silicon portions are delineated by photolithography and dry etching. Dry etching is carried out in SF.sub.6 -Cl.sub.2 /He at a low power density of about 0.1 to 0.3 watts/cm.sup.2. The remaining portions of polycrystalline silicon layer are subjected to a thermal oxidation at a temperature of about 800.degree. C. during which controllable quantities of the polycrystalline silicon are consumed. After removal of the thermally grown oxide, polycrystalline silicon portions are obtained with length and thickness dimensions reduced by a desired amount. If polycrystalline silicon portions are to be reduced only in length, the horizontal surfaces of these portions are protected during oxidation by a cap. The cap may include a several nm thick silicon nitride layer which is arranged on a silicon dioxide stress-relieve layer. The method is particularly useful in forming a submicrometer length gate electrode of a field effect transistor.
摘要翻译：描述了一种用于制造具有亚微米长度器件元件的半导体集成电路结构的方法，其中在半导体衬底中形成表面隔离图案以限定被指定为容纳器件的区域。第一绝缘化合物层形成在半导体衬底的被指定为部分栅极电介质的表面上。随后，在化合物层上沉积多晶硅层。多晶硅层通过磷离子注入重掺杂并在约850℃以下退火。多晶硅部分通过光刻和干法刻蚀来描绘。在SF6-Cl2 / He中以约0.1至0.3瓦特/平方厘米的低功率密度进行干蚀刻。多晶硅层的剩余部分在约800℃的温度下进行热氧化，在此期间消耗可控量的多晶硅。在去除热生长的氧化物之后，获得长度和厚度尺寸减小期望量的多晶硅部分。如果仅在长度上减少多晶硅部分，则这些部分的水平表面在通过盖子氧化时被保护。盖可以包括布置在二氧化硅应力释放层上的数nm厚的氮化硅层。该方法在形成场效应晶体管的亚微米长栅极电极时特别有用。

4. 发明授权

US4589952A Method of making trenches with substantially vertical sidewalls in silicon through reactive ion etching 失效
标题翻译：通过反应离子蚀刻在硅中制造具有基本垂直侧壁的沟槽的方法
公开(公告)号：US4589952A
公开(公告)日：1986-05-20
申请号：US670463
申请日：1984-11-09
申请人： Uwe Behringer , Johann Greschner , Hans-Joachim Trumpp
发明人： Uwe Behringer , Johann Greschner , Hans-Joachim Trumpp
IPC分类号： H01L21/302 , G03F1/20 , G03F7/09 , H01L21/027 , H01L21/3065 , H01L21/308 , H01L21/311
CPC分类号： G03F1/20 , G03F7/094 , H01L21/0271 , H01L21/3065 , H01L21/3081 , H01L21/31138
摘要： A method of making trenches having substantially vertical sidewalls in a silicon substrate using a three level mask comprising a thick photoresist layer, a silicon nitride layer and a thin photoresist layer. Openings are formed in the thin photoresist layer and silicon nitride layer by reactive ion etching in CF.sub.4. The openings are continued through the thick photoresist by etching in an atmosphere containing oxygen. The exposed surface of the silicon substrate is then etched in a CF.sub.4 atmosphere containing a low concentration of fluorine. Also disclosed is a method of making an electron beam transmission mask wherein the openings are made using the three level mask and reactive ion etching of silicon using the etching technique of the invention.
摘要翻译：一种使用三层掩模制造在硅衬底中具有基本上垂直侧壁的沟槽的方法，所述三层掩模包括厚的光致抗蚀剂层，氮化硅层和薄的光致抗蚀剂层。在CF4中通过反应离子蚀刻在薄的光致抗蚀剂层和氮化硅层中形成开口。通过在含氧的气氛中进行蚀刻，继续穿过厚的光致抗蚀剂。然后将硅衬底的暴露表面在含有低浓度氟的CF 4气氛中进行蚀刻。还公开了一种制造电子束透射掩模的方法，其中使用本发明的蚀刻技术使用三电平掩模和硅的反应离子蚀刻来制造开口。

5. 发明授权

US4980317A Method of producing integrated semiconductor structures comprising field-effect transistors with channel lengths in the submicron range using a three-layer resist system 失效
标题翻译：使用三层抗蚀剂体系制造包含具有亚微米范围的沟道长度的场效应晶体管的集成半导体结构的方法
公开(公告)号：US4980317A
公开(公告)日：1990-12-25
申请号：US326352
申请日：1989-03-21
申请人： Otto Koblinger , Reinhold Muhl , Hans-Joachim Trumpp
发明人： Otto Koblinger , Reinhold Muhl , Hans-Joachim Trumpp
IPC分类号： H01L21/302 , H01L21/027 , H01L21/28 , H01L21/30 , H01L21/3065
CPC分类号： H01L21/0271 , H01L21/28123 , Y10S148/051 , Y10S148/137 , Y10S438/947 , Y10S438/95 , Y10S438/97
摘要： Disclosed is a method of producing an integrated semiconductor structure, comprising components with dimensions in the submicron range, wherein a three-layer resist system is used to produce a polymer or resist mask. The polymer or resist mask thus produced is used to etch a layer of polysilicon on the semiconductor substrate. The method is characterized in that the pattern, produced conventionally in the top layer of the three-layer resist and including an angle
摘要翻译：公开了一种制造集成半导体结构的方法，其包括尺寸在亚微米范围内的组分，其中使用三层抗蚀剂体系来制备聚合物或抗蚀剂掩模。由此产生的聚合物或抗蚀剂掩模用于蚀刻半导体衬底上的多晶硅层。该方法的特征在于，通常在三层抗蚀剂的顶层中产生并且包括角度约90°的图案通过RIE使用CF 4转移到等离子体氮化物的中心层和通过RIE，使用氧气，到底部抗蚀剂或聚合物层。在现有技术的方法中，随后在氧气中进行横向蚀刻以将掩模的尺寸减小所需量。本发明的改进方法提供了首先要去除的等离子体氮化物掩模，如果需要，使用氧气中的平面步骤来增加掩模结构中的正角度，然后使后一结构在氧气中横向蚀刻以减少其尺寸按所需数量。当掩模中的角度<90°时，可以选择横向蚀刻的参数，使得蚀刻工艺在很大程度上是各向异性的，因此可以准确且容易地确定。结果，可以在蚀刻周期期间精确地调整横向蚀刻的绝对量。随着阴影等离子体氮化物在横向蚀刻之前被去除，相邻结构对横向蚀刻的影响大大降低。由此产生的掩模用于蚀刻多晶硅层结构，其角度确保在后续工艺步骤和离子注入中产生的间隔物的良好定义，这两者确定场效应晶体管的有效沟道长度。

6. 发明授权

US4502914A Method of making structures with dimensions in the sub-micrometer range 失效
标题翻译：制造尺寸在亚微米范围内的结构的方法
公开(公告)号：US4502914A
公开(公告)日：1985-03-05
申请号：US546612
申请日：1983-10-28
申请人： Hans-Joachim Trumpp , Johann Greschner
发明人： Hans-Joachim Trumpp , Johann Greschner
IPC分类号： H01L21/302 , C23F4/00 , H01L21/033 , H01L21/3065 , H01L21/308 , H01L21/76 , H01L21/762 , H01L21/306 , B29C17/08 , B44C1/22 , C03C15/00
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/76224 , Y10S438/947
摘要： Following the method of making structures with dimensions in the submicrometer range, structures of a polymeric layer with horizontal and substantially vertical surfaces are first made on a substrate. Thereupon, a silicon nitride or oxide layer is plasma deposited. This layer is subjected to reactive ion etching methods in such a manner that its horizontal regions and the polymeric structures are removed, with merely the narrow regions of the silicon nitride or oxide layer that had originally been arranged adjacent the vertical surfaces of the polymeric structures remaining. In the case of positive lithography, the silicon nitride or oxide walls are converted into a mask with the same dimensions but consisting of a different mask material. In the case of negative lithography the silicon nitride or oxide walls are converted in a mask reversal process into openings in a mask material layer through which by means of reactive ion etching vertical trenches approximately 0.5 .mu.m deep can be etched in the silicon substrate. The trenches are filled by thermal oxidation or with a synthetic material as e.g. polyimide. The method as disclosed by the invention can also be applied to other processes than recessed isolation in semiconductor technology.
摘要翻译：按照制造尺寸在亚微米范围内的结构的方法，首先在基底上制造具有水平和基本垂直表面的聚合物层的结构。因此，氮化硅或氧化物层被等离子体沉积。对该层进行反应离子蚀刻方法，使其水平区域和聚合物结构被去除，仅仅原本邻近聚合物结构的垂直表面的氮化硅或氧化物层的窄区域保留。在正光刻的情况下，氮化硅或氧化物壁被转换成具有相同尺寸的掩模，但由不同的掩模材料组成。在负光刻的情况下，氮化硅或氧化物壁在掩模反转工艺中转换成掩模材料层中的开口，通过反应离子蚀刻，可以在硅衬底中蚀刻大约0.5μm深的垂直沟槽。沟槽通过热氧化或用例如合成材料填充。聚酰亚胺。本发明公开的方法也可应用于半导体技术中的凹陷隔离以外的其它工艺。

7. 发明授权

US5055383A Process for making masks with structures in the submicron range 失效
标题翻译：用于制作带有结构的遮罩的方法
公开(公告)号：US5055383A
公开(公告)日：1991-10-08
申请号：US420870
申请日：1989-10-12
申请人： Otto Koblinger , Klaus Meissner , Reinhold Muhl , Hans-Joachim Trumpp , Werner Zapka
发明人： Otto Koblinger , Klaus Meissner , Reinhold Muhl , Hans-Joachim Trumpp , Werner Zapka
IPC分类号： G03F1/08 , G03F7/00 , G03F7/09 , H01L21/027 , H01L21/30 , H01L21/306 , H01L21/3065 , H01L21/308 , H01L21/311
CPC分类号： G03F7/0035 , G03F7/094 , H01L21/0271 , H01L21/30608 , H01L21/3065 , H01L21/3081 , H01L21/31144
摘要： In the course of the process for making masks with structures in the submicrometer range, initially structures of photoresist or polymer material with horizontal and substantially vertical sidewalls are produced on a silicon substrate covered with an oxide layer. This is followed by a layer of silicon nitride which is deposited by LPCVD. The resultant structure is planarized with a photoresist which is etched back until the start of the vertical edges of the sidewall coating formed by the nitride layer is bared on the photoresist structures. In a photolithographic step, a trimming mask is produced on the surface of the nitride layer and the planarizing resist. The bared regions of the nitride layer are then removed by isotropic etching. The dimensions A-B of the openings defined after removal of the nitride layer from the vertical surfaces of the photoresist structures are transferred to the oxide layer by anisotropic etching. Concurrently with these structures of minimum line width, registration marks are generated which allow the adjustment necessary for a further photolithographic step to be carried out with maximum accuracy. After removal of the trimming mask, the planarizing resist, the photoresist structures and the remainder of the nitride layer, structures with coarser line widths are defined in a further photolithographic step, which are also transferred to the oxide layer. Using the oxide layer as a mask, trenches of the desired depth are produced in the silicon substrate by anisotropic etching. The mask is thinned by anisotropic etching, and the oxide layers are removed from the front and the back side by wet etching.
摘要翻译：在制造具有亚微米范围内的结构的掩模的过程中，最初在被氧化物层覆盖的硅衬底上产生具有水平和基本垂直侧壁的光致抗蚀剂或聚合物材料的结构。之后是通过LPCVD沉积的一层氮化硅。所得到的结构被蚀刻后的光致抗蚀剂平坦化，直到由氮化物层形成的侧壁涂层的垂直边缘的开始在光致抗蚀剂结构上露出。在光刻步骤中，在氮化物层和平坦化抗蚀剂的表面上制造修整掩模。然后通过各向同性蚀刻除去氮化物层的裸露区域。在从光致抗蚀剂结构的垂直表面去除氮化物层之后限定的开口的尺寸A-B通过各向异性蚀刻转移到氧化物层。与最小线宽度的这些结构同时产生对准标记，其允许以最大精度执行进一步的光刻步骤所必需的调整。在去除修剪掩模之后，在另外的光刻步骤中限定平坦化抗蚀剂，光致抗蚀剂结构和氮化物层的其余部分，具有较宽线宽的结构也被转移到氧化物层。使用氧化物层作为掩模，通过各向异性蚀刻在硅衬底中产生所需深度的沟槽。通过各向异性蚀刻使掩模变薄，并且通过湿蚀刻从前侧和后侧去除氧化物层。

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