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1. 发明申请

US20170070193A1 RF Power Amplifier with Post-Distortion Linearizer 审中-公开
标题翻译：具有后失真线性化的RF功率放大器
公开(公告)号：US20170070193A1
公开(公告)日：2017-03-09
申请号：US14948380
申请日：2015-11-22
申请人： Ying-Zong Juang , Hann-Huei Tsai , Po-Chang Wu , Kuei-Cheng Lin , Chih-Yuan Yeh , Hwann-Kaeo Chiou
发明人： Ying-Zong Juang , Hann-Huei Tsai , Po-Chang Wu , Kuei-Cheng Lin , Chih-Yuan Yeh , Hwann-Kaeo Chiou
IPC分类号： H03F1/02 , H03F3/193 , H03F3/21 , H03F1/32
CPC分类号： H03F3/211 , H03F1/0261 , H03F1/3205 , H03F3/193 , H03F2200/432 , H03F2200/451 , H03F2201/3215 , H03F2203/21106
摘要： The invention provides an RF power amplifier with post-distortion linearizer. The power amplifier includes a main amplifier, an auxiliary amplifier and a phase compensator. The first amplifier has a first input end and a first output end and operates in class A or AB. The auxiliary amplifier has a second input end and a second output end and operates in class B or C. The second output end connects the first output end to form a signal output end. The phase compensator has a third input end and a third output end and compensates a phase difference between the main and auxiliary amplifiers to make outputs of the two amplifiers opposite in phase. The third output end connects the second input end. The third input end connects the first input end to form a signal input end.
摘要翻译：本发明提供一种具有后失真线性化的RF功率放大器。功率放大器包括主放大器，辅助放大器和相位补偿器。第一放大器具有第一输入端和第一输出端，并且在A或AB类中工作。辅助放大器具有第二输入端和第二输出端，并且在B或C类中工作。第二输出端连接第一输出端以形成信号输出端。相位补偿器具有第三输入端和第三输出端，并补偿主放大器和辅助放大器之间的相位差，使两个放大器的输出相位相反。第三输出端连接第二输入端。第三输入端连接第一输入端以形成信号输入端。

2. 发明申请

US20130146899A1 CMOS SENSOR WITH IMAGE SENSING UNIT INTEGRATED THEREIN 审中-公开
标题翻译： CMOS传感器与图像感应单元集成在一起
公开(公告)号：US20130146899A1
公开(公告)日：2013-06-13
申请号：US13408356
申请日：2012-02-29
申请人： Ying-Zong JUANG , Hann-Huei Tsai , Hsin-Hao Liao , Chen-Fu Lin
发明人： Ying-Zong JUANG , Hann-Huei Tsai , Hsin-Hao Liao , Chen-Fu Lin
IPC分类号： H01L33/02
CPC分类号： G01N21/00 , G01N27/128 , H01L25/167 , H01L2924/0002 , H01L2924/00
摘要： A complementary metal-oxide semiconductor (CMOS) sensor with an image sensing unit integrated therein is provided. The CMOS sensor includes a first substrate, a CMOS circuit, and a sensing device. The first substrate has the image sensing unit formed thereon. The CMOS circuit is disposed on the first substrate and has a receiving space. The sensing device is disposed in the receiving space. The image sensing unit is located at a position from which the image sensing unit can monitor the sensing device. Accordingly, the image sensing unit monitors the sensing device by sensing its image.
摘要翻译：提供了具有集成在其中的图像感测单元的互补金属氧化物半导体（CMOS）传感器。 CMOS传感器包括第一衬底，CMOS电路和感测装置。第一基板具有形成在其上的图像感测单元。 CMOS电路设置在第一基板上并具有接收空间。感测装置设置在接收空间中。图像感测单元位于图像感测单元可以从该位置监测感测装置的位置。因此，图像感测单元通过感测其图像监视感测装置。

3. 发明授权

US08451078B2 CMOS-MEMS switch structure 有权
标题翻译： CMOS-MEMS开关结构
公开(公告)号：US08451078B2
公开(公告)日：2013-05-28
申请号：US13160742
申请日：2011-06-15
申请人： You-Liang Lai , Ying-Zong Juang , Hann-Huei Tsai , Sheng-Hsiang Tseng , Chin-Fong Chiu
发明人： You-Liang Lai , Ying-Zong Juang , Hann-Huei Tsai , Sheng-Hsiang Tseng , Chin-Fong Chiu
IPC分类号： H01H51/22 , H01H57/00
CPC分类号： H01H1/0036 , H01H1/20 , H01H2001/0052 , H01H2001/0057 , H01H2001/0078 , H01H2061/006 , H01L27/0617
摘要： A CMOS-MEMS switch structure is disclosed. The CMOS-MEMS switch structure includes a first substrate, a second substrate, a first cantilever beam, and a second cantilever beam. The first and second substrates are positioned opposite each other. The first cantilever beam is provided on the first substrate, extends from the first substrate toward the second substrate, and bends downward. Likewise, the second cantilever beam is provided on the second substrate, extends from the second substrate toward the first substrate, and bends downward. The first and second substrates are movable toward each other to connect a first top surface of the first cantilever beam and a second top surface of the second cantilever beam, and away from each other so that the first top surface of the first cantilever beam and the second top surface of the second cantilever beam are disconnected, thereby closing or opening the CMOS-MEMS switch structure.
摘要翻译：公开了一种CMOS-MEMS开关结构。 CMOS-MEMS开关结构包括第一基板，第二基板，第一悬臂梁和第二悬臂梁。第一和第二基板彼此相对定位。第一悬臂梁设置在第一基板上，从第一基板朝向第二基板延伸，并向下弯曲。类似地，第二悬臂梁设置在第二基板上，从第二基板朝向第一基板延伸并向下弯曲。第一和第二基板可彼此移动以将第一悬臂梁的第一顶表面和第二悬臂梁的第二顶表面彼此远离，以使第一悬臂梁的第一顶表面和第二悬臂梁的第二顶表面被断开，从而关闭或打开CMOS-MEMS开关结构。

4. 发明申请

US20110117747A1 METHOD OF FABRICATING SINGLE CHIP FOR INTEGRATING FIELD-EFFECT TRANSISTOR INTO MEMS STRUCTURE 审中-公开
标题翻译：将场效应晶体管整合到MEMS结构中的制造单芯片的方法
公开(公告)号：US20110117747A1
公开(公告)日：2011-05-19
申请号：US12652068
申请日：2010-01-05
申请人： Chin-Long Wey , Chin-Fong Chiu , Ying-Zong Juang , Hann-Huei Tsai , Sheng-Hsiang Tseng , Hsin-Hao Liao
发明人： Chin-Long Wey , Chin-Fong Chiu , Ying-Zong Juang , Hann-Huei Tsai , Sheng-Hsiang Tseng , Hsin-Hao Liao
IPC分类号： H01L21/3065
CPC分类号： B81C1/00246 , B81B2207/015 , B81C2201/014 , B81C2203/0714 , B81C2203/0742 , H01L23/522 , H01L27/0617 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a single chip for integrating a field-effect transistor into a microelectromechanical systems (MEMS) structure is provided. The method includes the steps of: providing a substrate having thereon at least one transistor structure, a MEMS structure and a blocking structure, wherein the blocking structure encircles the MEMS structure to separate the MEMS structure from the transistor structure; forming a masking layer for covering the transistor structure, the MEMS structure and the blocking structure; forming a patterned photoresist layer on the masking layer; performing a first etching process by using the patterned photoresist layer to remove the masking layer on the MEMS structure; and performing a second etching process by removing a portion of the MEMS structure to form a plurality of microstructures such that a relative motion among the microstructures takes place in a direction perpendicular to the substrate.
摘要翻译：提供了一种制造用于将场效应晶体管集成到微机电系统（MEMS）结构中的单个芯片的方法。该方法包括以下步骤：提供其上具有至少一个晶体管结构的基板，MEMS结构和阻挡结构，其中所述阻挡结构环绕所述MEMS结构以将所述MEMS结构与所述晶体管结构分离; 形成用于覆盖晶体管结构，MEMS结构和阻挡结构的掩模层; 在掩模层上形成图案化的光致抗蚀剂层; 通过使用图案化的光致抗蚀剂层去除MEMS结构上的掩模层来执行第一蚀刻工艺; 以及通过去除所述MEMS结构的一部分以形成多个微观结构来执行第二蚀刻工艺，使得所述微结构之间的相对运动在垂直于所述衬底的方向上发生。

5. 发明申请

US20100099582A1 Biochip Package Structure 审中-公开
标题翻译：生物芯片封装结构
公开(公告)号：US20100099582A1
公开(公告)日：2010-04-22
申请号：US12336855
申请日：2008-12-17
申请人： Chin-Fong Chiu , Ying-Zong Juang , Hann-huei Tsai , Chen-Fu Lin
发明人： Chin-Fong Chiu , Ying-Zong Juang , Hann-huei Tsai , Chen-Fu Lin
IPC分类号： C40B60/12
CPC分类号： C40B60/12 , B01L3/502707 , B01L3/502715 , B01L2300/0645 , B01L2300/0816 , B01L2400/0439 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2924/16195 , H01L2924/16235 , H01L2924/1815 , H01L2924/00014 , H01L2924/00
摘要： A biochip package structure is provided. The biochip package structure includes a substrate, a biochip, at least one wire, and a molding compound. The substrate has a circuit unit electrically connected, by wiring, to the biochip defined with a sensing region. The molding compound covers the wire but leaves the sensing region of the biochip exposed, allowing a cavity to be formed in the sensing region. The cavity delivers a biomedical sample. The biomedical sample reacts in the sensing region. Thus, the biochip package structure is applicable to various medical and biochemical assays.
摘要翻译：提供了生物芯片封装结构。生物芯片封装结构包括基片，生物芯片，至少一根丝线和模塑料。衬底具有通过布线电连接到由感测区域限定的生物芯片的电路单元。模制化合物覆盖线，但使生物芯片的感测区域暴露，允许在感测区域中形成空腔。空腔提供生物医学样品。生物医学样品在感测区域内反应。因此，生物芯片封装结构适用于各种医疗和生物化学测定。

6. 发明授权

US07214551B2 Multiple gate electrode linewidth measurement and photoexposure compensation method 有权
标题翻译：多栅电极线宽测量和曝光补偿方法
公开(公告)号：US07214551B2
公开(公告)日：2007-05-08
申请号：US10684855
申请日：2003-10-14
申请人： Jia-Ren Chen , Hung Che Hsiue , Hann Huei Tsai , Wei Hsiung Hsu
发明人： Jia-Ren Chen , Hung Che Hsiue , Hann Huei Tsai , Wei Hsiung Hsu
IPC分类号： H01L21/66
CPC分类号： G01R31/27 , G01R31/2831 , H01L27/0203 , H01L27/105 , H01L27/1052
摘要： A method for fabricating a semiconductor product first provides an embedded semiconductor product comprising: (1) a logic region having formed therein a logic field effect transistor device; (2) a memory region having formed therein a memory field effect transistor device; and (3) a kerf region having formed therein a kerf field effect transistor device. The method also provides for measuring for the embedded semiconductor product a gate electrode linewidth for each of the logic field effect transistor device, the memory field effect transistor device and the kerf field effect transistor device. The measured gate electrode linewidths may be compared among themselves or to specified target values for purposes photoexposure process control.
摘要翻译：一种制造半导体产品的方法首先提供一种嵌入式半导体产品，其包括：（1）逻辑区域，其中形成有逻辑场效应晶体管器件; （2）在其中形成有存储器场效应晶体管器件的存储区域; 和（3）在其中形成有切口场效应晶体管器件的切口区域。该方法还为嵌入式半导体产品测量每个逻辑场效应晶体管器件，存储器场效应晶体管器件和切角场效应晶体管器件的栅电极线宽。测量的栅电极线宽可以在它们之间进行比较，也可以用于光曝光过程控制的指定目标值。

7. 发明授权

US6103581A Method for producing shallow trench isolation structure 有权
标题翻译：生产浅沟隔离结构的方法
公开(公告)号：US6103581A
公开(公告)日：2000-08-15
申请号：US200552
申请日：1998-11-27
申请人： Chung-Te Lin , Chin-Hsiung Ho , Hann-Huei Tsai
发明人： Chung-Te Lin , Chin-Hsiung Ho , Hann-Huei Tsai
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A method for fabricating shallow trench isolation stricture wherein a surface oxide layer and a polycrystalline silicon buffer layer are formed on a semiconductor body. Openings are formed through the layers and into the body that constitute trenches. A lining oxide layer is formed on the trench and buffer layer surfaces. A thick oxide layer is deposited on the body to fill the trench, and the layer planarized by chemical-mechanical polishing. The exposed portions of the buffer layer are removed and the horizontal surface oxide layer portions removed by anisotropic etching.
摘要翻译：一种制造浅沟槽隔离狭缝的方法，其中在半导体本体上形成表面氧化物层和多晶硅缓冲层。开口形成穿过构成沟槽的各层和身体。在沟槽和缓冲层表面上形成衬里氧化物层。在氧化层上沉积厚的氧化层以填充沟槽，并通过化学机械抛光将层平坦化。去除缓冲层的露出部分，并通过各向异性蚀刻除去水平表面氧化物层部分。

8. 发明授权

US09548673B1 Master-slave voltage doubling full-wave rectifier for wireless power transfer system 有权
标题翻译：主从电压倍增全波整流器用于无线电力传输系统
公开(公告)号：US09548673B1
公开(公告)日：2017-01-17
申请号：US14948409
申请日：2015-11-23
申请人： Ying-Zong Juang , Hann-Huei Tsai , Po-Chang Wu , Kuei-Cheng Lin , Chih-Yuan Yeh
发明人： Ying-Zong Juang , Hann-Huei Tsai , Po-Chang Wu , Kuei-Cheng Lin , Chih-Yuan Yeh
IPC分类号： H02M7/04
CPC分类号： H02M7/04 , H02M7/103 , H02M7/217
摘要： The invention includes two parallel paths. A first path is composed of two contact ends of a first electronic switch and a first, third and fifth diodes, which connect in series. One contact end connects a first end of an AC source, and a control end connects a second end of the AC source. A second path is composed of two contact ends of a second electronic switch and a second, fourth and sixth diodes, which connect in series. One contact end connects the second end of the AC source, and a control end connects the first end of the AC source. The AC source is connected between the positive ends of the first and second diodes. The second end of the AC source separately connects negative ends of the first and third diodes through two capacitors. The first end of the AC source separately connects negative ends of the second and fourth diodes through another two capacitors. Negative ends of the fifth and sixth diodes connect together to form a voltage output end.
摘要翻译：本发明包括两条平行路径。第一路径由第一电子开关和串联连接的第一，第三和第五二极管的两个接触端组成。一个接触端连接AC电源的第一端，控制端连接AC电源的第二端。第二路径由第二电子开关和串联连接的第二，第四和第六二极管的两个接触端组成。一个接触端连接AC电源的第二端，控制端连接AC电源的第一端。 AC源连接在第一和第二二极管的正极之间。交流电源的第二端通过两个电容器将第一和第三二极管的负极分开连接。交流电源的第一端通过另外两个电容器将第二和第四二极管的负极分开连接。第五和第六二极管的负端连接在一起形成电压输出端。

9. 发明申请

US20120279838A1 CMOS-MEMS SWITCH STRUCTURE 有权
标题翻译： CMOS-MEMS开关结构
公开(公告)号：US20120279838A1
公开(公告)日：2012-11-08
申请号：US13160742
申请日：2011-06-15
申请人： You-Liang LAI , Ying-Zong JUANG , Hann-Huei TSAI , Sheng-Hsiang TSENG , Chin-Fong CHIU
发明人： You-Liang LAI , Ying-Zong JUANG , Hann-Huei TSAI , Sheng-Hsiang TSENG , Chin-Fong CHIU
IPC分类号： H01H59/00
CPC分类号： H01H1/0036 , H01H1/20 , H01H2001/0052 , H01H2001/0057 , H01H2001/0078 , H01H2061/006 , H01L27/0617
摘要： A CMOS-MEMS switch structure is disclosed. The CMOS-MEMS switch structure includes a first substrate, a second substrate, a first cantilever beam, and a second cantilever beam. The first and second substrates are positioned opposite each other. The first cantilever beam is provided on the first substrate, extends from the first substrate toward the second substrate, and bends downward. Likewise, the second cantilever beam is provided on the second substrate, extends from the second substrate toward the first substrate, and bends downward. The first and second substrates are movable toward each other to connect a first top surface of the first cantilever beam and a second top surface of the second cantilever beam, and away from each other so that the first top surface of the first cantilever beam and the second top surface of the second cantilever beam are disconnected, thereby closing or opening the CMOS-MEMS switch structure.
摘要翻译：公开了一种CMOS-MEMS开关结构。 CMOS-MEMS开关结构包括第一基板，第二基板，第一悬臂梁和第二悬臂梁。第一和第二基板彼此相对定位。第一悬臂梁设置在第一基板上，从第一基板朝向第二基板延伸，并向下弯曲。类似地，第二悬臂梁设置在第二基板上，从第二基板朝向第一基板延伸并向下弯曲。第一和第二基板可彼此移动以将第一悬臂梁的第一顶表面和第二悬臂梁的第二顶表面彼此远离，以使第一悬臂梁的第一顶表面和第二悬臂梁的第二顶表面被断开，从而关闭或打开CMOS-MEMS开关结构。

10. 发明授权

US08704580B2 Circuit sharing time delay integrator 有权
标题翻译：电路共享时延积分器
公开(公告)号：US08704580B2
公开(公告)日：2014-04-22
申请号：US13594559
申请日：2012-08-24
申请人： Chin-Fong Chiu , Hann-Huei Tsai , Wen-Hsu Chang , Chih-Cheng Hsieh , Kuo-Wei Cheng
发明人： Chin-Fong Chiu , Hann-Huei Tsai , Wen-Hsu Chang , Chih-Cheng Hsieh , Kuo-Wei Cheng
IPC分类号： G06G7/19
CPC分类号： G06G7/18 , H04N5/3743 , H04N5/37457
摘要： The present invention discloses a circuit sharing time delay integrator structure. The major composing elements of this circuit sharing time delay integrator structure are: a sharing circuit, a first control block, a plurality of second control blocks and a timing set generated by a timing generator circuit. The sharing circuit can be an OP-AMP, an active load, or any of a variety of combinations used in signal accumulation applications. With the implementation of the present invention to applications of signal accumulations, the necessity of an adder circuitry is eliminated, the overall circuitry and hence the total amount of transistors required when producing the integrated circuit is massively reduced, and thus a great cost reduction and better timing and power efficiency can all be thereof achieved.
摘要翻译：本发明公开了一种电路共享时延积分器结构。该电路共享时延积分器结构的主要组成要素是共享电路，第一控制块，多个第二控制块和由定时发生器电路产生的定时集。共享电路可以是OP-AMP，有源负载或用于信号积累应用中的各种组合中的任何一种。通过本发明实现信号积累的应用，消除了加法器电路的必要性，大大降低了整体电路和因此产生集成电路所需的晶体管总量，从而大大降低了成本定时和功率效率都可以实现。

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