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    • 3. 发明申请
    • Edge-Missing Detector Structure
    • 边缘缺失检测器结构
    • US20100277203A1
    • 2010-11-04
    • US12489624
    • 2009-06-23
    • Ting Hsu ChienChi Sheng LinChin-Long WeyChun-Ming HuangYing-Zong Juang
    • Ting Hsu ChienChi Sheng LinChin-Long WeyChun-Ming HuangYing-Zong Juang
    • H03K5/19
    • H03K5/19H03K5/1534H03L7/0891H03L7/10
    • An edge-missing detector structure includes a first detector, a first delay unit, a first logic gate, a second detector, a second delay unit, and a second logic gate. After being input separately into the edge-missing detector structure, a first reference signal and a first clock signal are detected by the first and second detectors and then subjected to cycle suppression by the first and second logic gates, respectively, so as to generate a second reference signal and a second clock signal which present a phase difference less than 2π. Moreover, the edge-missing detector structure generates a compensative current corresponding to the number of occurrences of cycle suppression. Thus, a phase-locked loop (PLL) using the edge-missing detector structure can avoid cycle slip problems and achieve fast acquisition of phase lock.
    • 边缘丢失检测器结构包括第一检测器,第一延迟单元,第一逻辑门,第二检测器,第二延迟单元和第二逻辑门。 在分别输入到边缘丢失检测器结构中之后,第一和第二检测器检测第一参考信号和第一时钟信号,然后分别由第一和第二逻辑门进行循环抑制,以产生 第二参考信号和呈现小于2&pgr的相位差的第二时钟信号。 此外,边缘丢失检测器结构产生对应于循环抑制的出现次数的补偿电流。 因此,使用边缘丢失检测器结构的锁相环(PLL)可以避免周期滑移问题并实现锁相的快速采集。