专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060079093A1 Method for fabricating semiconductor device using tungsten as sacrificial hard mask 有权
标题翻译：使用钨作为牺牲硬掩模制造半导体器件的方法
公开(公告)号：US20060079093A1
公开(公告)日：2006-04-13
申请号：US11149325
申请日：2005-06-10
申请人： Kwang-Ok Kim , Yun-Seok Cho , Seung-Chan Moon , Jin-Ki Jung , Sung-Kwon Lee , Jun-Hyeub Sun , Dong-Duk Lee , Jin-Woong Kim , Gyu-Han Yoon
发明人： Kwang-Ok Kim , Yun-Seok Cho , Seung-Chan Moon , Jin-Ki Jung , Sung-Kwon Lee , Jun-Hyeub Sun , Dong-Duk Lee , Jin-Woong Kim , Gyu-Han Yoon
IPC分类号： H01L21/461
CPC分类号： H01L21/76802 , H01L21/0332 , H01L21/28123 , H01L21/31116 , H01L21/31144 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L27/10894
摘要： The present invention relates to a method for fabricating a semiconductor device using tungsten as a sacrificial hard mask material. The method includes the steps of: forming a layer on an etch target layer; forming a photoresist pattern on the layer; etching the layer by using the photoresist pattern as an etch mask along with use of a plasma containing CHF3 gas to form a sacrificial hard mask; and etching the etch target layer by using at least the sacrificial hard mask as an etch mask, thereby obtaining a predetermined pattern.
摘要翻译：本发明涉及使用钨作为牺牲硬掩模材料制造半导体器件的方法。该方法包括以下步骤：在蚀刻目标层上形成层; 在该层上形成光致抗蚀剂图案; 通过使用光致抗蚀剂图案作为蚀刻掩模以及使用含有CHF 3 N 3气体的等离子体来蚀刻该层以形成牺牲硬掩模; 并且通过使用至少牺牲硬掩模作为蚀刻掩模来蚀刻蚀刻目标层，由此获得预定图案。

2. 发明授权

US06455380B2 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06455380B2
公开(公告)日：2002-09-24
申请号：US09735909
申请日：2000-12-14
申请人： Gyu Han Yoon
发明人： Gyu Han Yoon
IPC分类号： H01L21336
CPC分类号： H01L29/512 , H01L21/2255 , H01L29/1045 , H01L29/1083 , H01L29/66492 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device is disclosed, including: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a first gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a first region including one edge of the gate electrode; a second gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a second portion including the other edge of the gate electrode, the second gate insulating layer being thicker than the first gate insulating layer; a first impurity region formed in a predetermined portion of the semiconductor substrate, placed on both sides of the gate electrode; and a second impurity region formed in a predetermined portion of the semiconductor substrate, placed under the second gate insulating layer.
摘要翻译：公开了一种半导体器件，包括：半导体衬底; 形成在所述半导体衬底上的栅电极; 形成在所述栅极电极和半导体衬底之间并形成在包括所述栅电极的一个边缘的第一区域的第一栅极绝缘层; 形成在栅电极和半导体衬底之间的第二栅极绝缘层，并且形成在包括栅极电极的另一边缘的第二部分处，第二栅极绝缘层比第一栅极绝缘层厚; 形成在半导体衬底的预定部分中的第一杂质区，放置在栅电极的两侧; 以及形成在所述半导体衬底的预定部分中的第二杂质区，设置在所述第二栅绝缘层的下方。

3. 发明授权

US06238985B1 Semiconductor device and method for fabricating the same 有权
公开(公告)号：US06238985B1
公开(公告)日：2001-05-29
申请号：US09310334
申请日：1999-05-12
申请人： Gyu Han Yoon
发明人： Gyu Han Yoon
IPC分类号： H01L21336
CPC分类号： H01L29/512 , H01L21/2255 , H01L29/1045 , H01L29/1083 , H01L29/66492 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device is disclosed, including: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a first gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a first region including one edge of the gate electrode; a second gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a second portion including the other edge of the gate electrode, the second gate insulating layer being thicker than the first gate insulating layer; a first impurity region formed in a predetermined portion of the semiconductor substrate, placed on both sides of the gate electrode; and a second impurity region formed in a predetermined portion of the semiconductor substrate, placed under the second gate insulating layer.

4. 发明授权

US5952700A MOSFET device with unsymmetrical LDD region 失效
标题翻译：具有不对称LDD区域的MOSFET器件
公开(公告)号：US5952700A
公开(公告)日：1999-09-14
申请号：US957622
申请日：1997-10-24
申请人： Gyu Han Yoon
发明人： Gyu Han Yoon
IPC分类号： H01L21/225 , H01L21/336 , H01L29/10 , H01L29/78 , H01L29/76 , H01L31/062
CPC分类号： H01L29/512 , H01L21/2255 , H01L29/66492 , H01L29/66659 , H01L29/7835 , H01L29/1045 , H01L29/1083
摘要： A semiconductor device is disclosed, including: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a first gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a first region including one edge of the gate electrode; a second gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a second portion including the other edge of the gate electrode, the second gate insulating layer being thicker than the first gate insulating layer; a first impurity region formed in a predetermined portion of the semiconductor substrate, placed on both sides of the gate electrode; and a second impurity region formed in a predetermined portion of the semiconductor substrate, placed under the second gate insulating layer.
摘要翻译：公开了一种半导体器件，包括：半导体衬底; 形成在所述半导体衬底上的栅电极; 形成在所述栅极电极和半导体衬底之间并形成在包括所述栅电极的一个边缘的第一区域的第一栅极绝缘层; 形成在所述栅电极和半导体衬底之间的第二栅极绝缘层，并且形成在包括所述栅电极的另一边缘的第二部分处，所述第二栅极绝缘层比所述第一栅极绝缘层厚; 形成在半导体衬底的预定部分中的第一杂质区，放置在栅电极的两侧; 以及形成在所述半导体衬底的预定部分中的第二杂质区，设置在所述第二栅绝缘层的下方。

5. 发明授权

US07442648B2 Method for fabricating semiconductor device using tungsten as sacrificial hard mask 有权
标题翻译：使用钨作为牺牲硬掩模制造半导体器件的方法
公开(公告)号：US07442648B2
公开(公告)日：2008-10-28
申请号：US11149325
申请日：2005-06-10
申请人： Kwang-Ok Kim , Yun-Seok Cho , Seung-Chan Moon , Jin-Ki Jung , Sung-Kwon Lee , Jun-Hyeub Sun , Dong-Duk Lee , Jin-Woong Kim , Gyu-Han Yoon
发明人： Kwang-Ok Kim , Yun-Seok Cho , Seung-Chan Moon , Jin-Ki Jung , Sung-Kwon Lee , Jun-Hyeub Sun , Dong-Duk Lee , Jin-Woong Kim , Gyu-Han Yoon
IPC分类号： H01L21/302
CPC分类号： H01L21/76802 , H01L21/0332 , H01L21/28123 , H01L21/31116 , H01L21/31144 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L27/10894
摘要： The present invention relates to a method for fabricating a semiconductor device using tungsten as a sacrificial hard mask material. The method includes the steps of: forming a layer on an etch target layer; forming a photoresist pattern on the layer; etching the layer by using the photoresist pattern as an etch mask along with use of a plasma containing CHF3 gas to form a sacrificial hard mask; and etching the etch target layer by using at least the sacrificial hard mask as an etch mask, thereby obtaining a predetermined pattern.
摘要翻译：本发明涉及使用钨作为牺牲硬掩模材料制造半导体器件的方法。该方法包括以下步骤：在蚀刻目标层上形成层; 在该层上形成光致抗蚀剂图案; 通过使用光致抗蚀剂图案作为蚀刻掩模以及使用含有CHF 3 N 3气体的等离子体来蚀刻该层以形成牺牲性硬掩模; 并且通过使用至少牺牲硬掩模作为蚀刻掩模来蚀刻蚀刻目标层，由此获得预定图案。

6. 发明授权

US07282421B2 Methods for reducing a thickness variation of a nitride layer formed in a shallow trench isolation CMP process and for forming a device isolation film of a semiconductor device 有权
标题翻译：减少在浅沟槽隔离CMP工艺中形成的氮化物层的厚度变化并形成半导体器件的器件隔离膜的方法
公开(公告)号：US07282421B2
公开(公告)日：2007-10-16
申请号：US10998809
申请日：2004-11-30
申请人： Yong Soo Choi , Hyuk Kwon , Sang Hwa Lee , Geun Min Choi , Yong Wook Song , Gyu Han Yoon
发明人： Yong Soo Choi , Hyuk Kwon , Sang Hwa Lee , Geun Min Choi , Yong Wook Song , Gyu Han Yoon
IPC分类号： H01L21/76
CPC分类号： H01L21/31053 , H01L21/76224 , Y10S438/975
摘要： A method for reducing a thickness variation of a nitride layer in a shallow trench isolation (STI) CMP process is provided, the method including forming an active region pattern in an alignment key region of a scribe lane where a device isolation film is formed at an ISO level, and forming a dummy active region pattern substantially adjacent to a vernier key pattern in the scribe lane during formation of the vernier key pattern, wherein the dummy active region pattern is spaced apart from the vernier key pattern by a known distance. Preferably, the active region pattern and the dummy active region pattern are formed prior to the STI CMP process.
摘要翻译：提供了一种用于减小浅沟槽隔离（STI）CMP工艺中的氮化物层的厚度变化的方法，该方法包括在形成器件隔离膜的划线的对准键区域中形成有源区域图案 ISO水平，并且在形成游标键图案期间形成与划线中的游标键图案基本相邻的虚拟有源区域图案，其中虚拟有源区域图案与游标键图案间隔已知距离。优选地，在STI CMP处理之前形成有源区图案和伪有源区图案。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式