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1. 发明授权

US06993688B2 Data sector error tracking and correction mechanism 有权
公开(公告)号：US06993688B2
公开(公告)日：2006-01-31
申请号：US10071018
申请日：2002-02-07
申请人： Hui Su , Gregory P. Moller
发明人： Hui Su , Gregory P. Moller
IPC分类号： G06F11/00 , G11C29/00
CPC分类号： G11B20/1879 , G11B5/012 , G11B20/1816 , G11B2005/001 , G11B2020/183
摘要： A method is provided for reducing growth errors in disc drive. First, a number of sectors to be read is determined. Data is then read from all sectors of the number of sectors on a disc during a first disc revolution. Next, error sectors having a number of errors above a predetermined threshold are identified. The error sectors are then corrected and written to the disc during a second disc revolution. In addition, a disc drive having a controller for implementing the above method is provided.

2. 发明授权

US06421759B1 Single-cycle variable period buffer manager for disk controllers 失效
标题翻译：磁盘控制器的单周期可变周期缓冲管理器
公开(公告)号：US06421759B1
公开(公告)日：2002-07-16
申请号：US09596330
申请日：2000-06-16
申请人： Gregory P. Moller
发明人： Gregory P. Moller
IPC分类号： G06F1300
CPC分类号： G06F3/0613 , G06F3/0656 , G06F3/0676
摘要： The present invention relates generally to the field of disc controllers, and more specifically to an efficient buffer manager for a disc controller. A state machine in the buffer manager is provided which is responsive to a clock controlled by a single frequency base clock signal and a speed selection signal which indicates the speed of the buffer memory and which is designed to provide a base clock signal for the state machine having a fixed base period and an extended second portion of the cycle period which is extended to reflect the time of the RAMs cycle, plus the necessary time to allow for circuit delays and the like. Thus, different speed RAMs can be used in association with the buffer manager designed in this manner, while always controlling access for reading and writing to the RAM during a single complete cycle of the buffer manager. This allows for direct gating of all control signals to the buffer RAM, simplifying the design of the buffer memory controller and its associated logic. The buffer manager synchronizes all requests from various sources, and utilizes a single clock cycle of varying periods to accommodate all speeds of RAMs with just one base synthesizer frequency in order to reduce the cost and maximize simplicity oft he buffer manager design.
摘要翻译：本发明一般涉及盘控制器的领域，更具体地说涉及一种用于盘控制器的高效缓冲管理器。提供缓冲器管理器中的状态机，其响应于由单个频率基准时钟信号控制的时钟和指示缓冲存储器的速度的速度选择信号，其被设计为为状态机提供基本时钟信号具有固定的基准周期和延长的周期的延长的第二部分，以反映RAM周期的时间，加上允许电路延迟等的必要时间。因此，可以与以这种方式设计的缓冲器管理器相关联地使用不同速度的RAM，而在缓冲器管理器的单个完整周期期间总是控制对RAM的读取和写入的访问。这允许将所有控制信号直接门控到缓冲RAM，简化了缓冲存储器控制器及其相关逻辑的设计。缓冲器管理器将来自各种来源的所有请求同步，并且利用不同周期的单个时钟周期来容纳具有仅一个基本合成器频率的RAM的所有速度，以便降低成本并最大化缓冲器管理器设计的简单性。

3. 发明授权

US07206990B2 Data sector error handling mechanism 有权
标题翻译：数据扇区错误处理机制
公开(公告)号：US07206990B2
公开(公告)日：2007-04-17
申请号：US10379295
申请日：2003-03-03
申请人： Hui Su , Gregory P. Moller
发明人： Hui Su , Gregory P. Moller
IPC分类号： G11C29/00
CPC分类号： G11B20/1816 , G11B5/012 , G11B20/1879 , G11B2005/001 , G11B2020/183
摘要： A method is provided for handling errors in a data storage system. The method includes determining a number of sectors to be accessed. Also, all sectors from the number of sectors are accessed during a first access routine. Next, error sectors are identified and the error sectors are accessed during a second access routine.
摘要翻译：提供了一种处理数据存储系统中的错误的方法。该方法包括确定要访问的扇区的数量。此外，在第一次访问例程期间访问来自扇区数的所有扇区。接下来，识别错误扇区，并且在第二访问例程期间访问错误扇区。

4. 发明授权

US6157985A Single-cycle variable period buffer manager for disk controllers 失效
标题翻译：磁盘控制器的单周期可变周期缓冲管理器
公开(公告)号：US6157985A
公开(公告)日：2000-12-05
申请号：US951619
申请日：1997-10-16
申请人： Gregory P. Moller
发明人： Gregory P. Moller
IPC分类号： G06F3/06 , G06F12/00
CPC分类号： G06F3/0613 , G06F3/0656 , G06F3/0676
摘要： The present invention relates generally to the field of disc controllers, and more specifically to an efficient buffer manager for a disc controller. A state machine in the buffer manager is provided which is responsive to a clock controlled by a single frequency base clock signal and a speed selection signal which indicates the speed of the buffer memory and which is designed to provide a base clock signal for the state machine having a fixed base period and an extended second portion of the cycle period which is extended to reflect the time of the RAMs cycle, plus the necessary time to allow for circuit delays and the like. Thus, different speed RAMs can be used in association with the buffer manager designed in this manner, while always controlling access for reading and writing to the RAM during a single complete cycle of the buffer manager. This allows for direct gating of all control signals to the buffer RAM, simplifying the design of the buffer memory controller and its associated logic. The buffer manager synchronizes all requests from various sources, and utilizes a single clock cycle of varying periods to accommodate all speeds of RAMs with just one base synthesizer frequency in order to reduce the cost and maximize simplicity of the buffer manager design.
摘要翻译：本发明一般涉及盘控制器的领域，更具体地说涉及一种用于盘控制器的高效缓冲管理器。提供缓冲器管理器中的状态机，其响应于由单个频率基准时钟信号控制的时钟和指示缓冲存储器的速度的速度选择信号，其被设计为为状态机提供基本时钟信号具有固定的基准周期和延长的周期的延长的第二部分，以反映RAM周期的时间，加上允许电路延迟等的必要时间。因此，可以与以这种方式设计的缓冲器管理器相关联地使用不同速度的RAM，而在缓冲器管理器的单个完整周期期间总是控制对RAM的读取和写入的访问。这允许将所有控制信号直接门控到缓冲RAM，简化了缓冲存储器控制器及其相关逻辑的设计。缓冲管理器将来自各种来源的所有请求同步，并且利用不同周期的单个时钟周期来容纳具有一个基本合成器频率的RAM的所有速度，以便降低成本并最大化缓冲器管理器设计的简单性。

5. 发明授权

US06693753B2 Disc sequencer supporting pipelined and non-pipelined read 有权
标题翻译：支持流水线和非流水线读取的光盘顺控程序
公开(公告)号：US06693753B2
公开(公告)日：2004-02-17
申请号：US09872409
申请日：2001-06-01
申请人： Hui Su , Gregory P. Moller
发明人： Hui Su , Gregory P. Moller
IPC分类号： G11B509
CPC分类号： G11B20/10 , G06F3/0607 , G06F3/0656 , G06F3/0674 , G11B5/012 , G11B20/10009
摘要： A disc sequencer incorporating parallel state machines to support both pipelined and non-pipelined read modes is disclosed. The parallel state machines include a first state machine and a second state machine for controlling whether data are read from a disc media and transferred to a buffer via a channel interface coupled to a read/write channel. Data may be read through the read/write channel in either pipelined or non-pipelined mode. If an operational state of either state machine is active, then the transfer of data between a read/write head accessing the media and the buffer is enabled. The operational state of the first state machine is dependent on the operational state of the second state machine such that if the second state machine is active, the operational state of the first machine will go active on the following clock period.
摘要翻译：公开了一种包含并行状态机以支持流水线和非流水线读取模式的盘定序器。并行状态机包括第一状态机和第二状态机，用于控制数据是否从盘介质读取并经由耦合到读/写通道的通道接口传送到缓冲器。数据可以以流水线或非流水线方式通过读/写通道进行读取。如果任一状态机的运行状态为活动状态，则可以在访问介质的读/写头和缓冲区之间传输数据。第一状态机的操作状态取决于第二状态机的操作状态，使得如果第二状态机处于活动状态，则第一机器的操作状态将在随后的时钟周期内变为活动状态。

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