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1. 发明授权

US06228706B1 Vertical DRAM cell with TFT over trench capacitor 失效
标题翻译：具有TFT沟槽电容器的垂直DRAM单元
公开(公告)号：US06228706B1
公开(公告)日：2001-05-08
申请号：US09384298
申请日：1999-08-26
申请人： David Vaclav Horak , Rick Lawrence Mohler , Gorden Seth Starkey, Jr.
发明人： David Vaclav Horak , Rick Lawrence Mohler , Gorden Seth Starkey, Jr.
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/1087 , H01L27/10876
摘要： A memory cell which comprises a substrate having a top surface; a capacitor extending vertically into the substrate for storing a voltage representing a datum, said capacitor occupying a geometrically shaped horizontal area; a transistor formed above the capacitor and occupying a horizontal area substantially equal to the geometrically shaped horizontal area, and having a vertical device depth, for establishing an electrical connection with the capacitor, in response to a control signal, for reading from, and writing to, the capacitor, wherein the transistor includes a gate formed near the periphery of said horizontal device area and having a vertical depth approximately equal to the vertical device depth; an oxide layer on an inside surface of the gate; a conductive body formed inside the oxide layer, said conductive body having a top surface and a bottom surface and a vertical depth approximately equal to the vertical device depth; and diffusion regions in the body near the top and bottom surfaces and a method of manufacturing the same is provided.
摘要翻译：一种记忆单元，包括具有顶表面的基底; 电容器垂直延伸到基板中，用于存储表示基准的电压，所述电容器占据几何形状的水平面积; 晶体管，形成在电容器上方并且占据基本上等于几何形状水平面积的水平面积，并且具有垂直器件深度，用于响应于控制信号与电容器建立电连接，用于读取和写入所述电容器，其中所述晶体管包括形成在所述水平装置区域的周边附近并具有大约等于垂直装置深度的垂直深度的栅极; 栅极内表面上的氧化物层; 形成在所述氧化物层内部的导电体，所述导电体具有顶表面和底表面以及垂直深度近似等于垂直装置深度; 并且在顶部和底部表面附近的主体中的扩散区域及其制造方法。

2. 发明授权

US5665629A Four transistor SRAM process 失效
标题翻译：四晶体管SRAM工艺
公开(公告)号：US5665629A
公开(公告)日：1997-09-09
申请号：US514016
申请日：1995-08-11
申请人： Bomy Able Chen , Gorden Seth Starkey
发明人： Bomy Able Chen , Gorden Seth Starkey
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/1112
摘要： A SRAM cell with cross-coupled transistors, a pair of transfer gate transistors and a pair of load resistors is manufactured by forming a plurality of field effect transistors in a silicon substrate. In one embodiment, the transistors are formed in an SOI substrate to improve soft-error resistance. An insulator layer is deposited over the source, drain and gate contacts (device contact areas), hole openings are etched into the insulating layer to expose a plurality of device contact areas. A highly resistive layer is patterned to substantially cover and in contact with some selected contact hole openings and device contact areas. A conductive material is deposited into all of the contact hole openings so as to substantially over-fill the contact hole openings and make electrical contact with the device contacts and patterned resistive layer. A planarizing process used to remove the conductive material and the resistive layer outside of the contact holes, thus forming all contact studs with selected studs having integrated resistors. The contact studs are interconnected among themselves and connected to a power bus, a ground, word and bit lines to form the SRAM cell.
摘要翻译：通过在硅衬底中形成多个场效应晶体管来制造具有交叉耦合晶体管的SRAM单元，一对传输栅晶体管和一对负载电阻器。在一个实施例中，晶体管形成在SOI衬底中以改善软错误电阻。在源极，漏极和栅极触点（器件接触区域）上沉积绝缘体层，孔绝缘层中蚀刻出孔开口以露出多个器件接触区域。图案化高电阻层以基本上覆盖并接触一些所选择的接触孔开口和设备接触区域。导电材料沉积到所有接触孔开口中，以便基本上填充接触孔开口并与器件触点和图案化电阻层电接触。用于去除接触孔外部的导电材料和电阻层的平面化处理，从而形成具有集成电阻器的所选螺柱的所有触头螺柱。接触柱在它们之间互连并连接到电源总线，接地，字和位线以形成SRAM单元。

3. 发明授权

US5654238A Method for etching vertical contact holes without substrate damage caused by directional etching 失效
标题翻译：用于蚀刻垂直接触孔的方法，无定向蚀刻造成的基板损伤
公开(公告)号：US5654238A
公开(公告)日：1997-08-05
申请号：US510718
申请日：1995-08-03
申请人： John Edward Cronin , Michael David Potter , Gorden Seth Starkey
发明人： John Edward Cronin , Michael David Potter , Gorden Seth Starkey
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76816
摘要： A method of etching vias without directional etching damage to the substrate. A pattern image is formed on an insulating layer of known thickness over a substrate. A conformal layer is formed on the pattern image. A vertical contact hole through the conformal layer and into the insulating layer is produced by directional etching. The directional etch also leaves conformal sidewall spacers of a defined width. The depth of the vertical contact hole is equal to the thickness of the insulating layer minus the width of the conformal spacer. The insulating layer is then removed by an isotropic wet etch to achieve a near vertical edge contact hole without directional etching damage to the substrate. The sidewall spacers may also be removed by etching prior to removal of the insulating layer.
摘要翻译：蚀刻通孔而不对基板进行定向蚀刻损伤的方法。图案图像形成在衬底上已知厚度的绝缘层上。在图案图像上形成保形层。通过定向蚀刻产生通过共形层和绝缘层的垂直接触孔。定向蚀刻还留下具有限定宽度的共形侧壁间隔物。垂直接触孔的深度等于绝缘层的厚度减去保形间隔物的宽度。然后通过各向同性的湿蚀刻去除绝缘层，以实现近似垂直的边缘接触孔，而不会对衬底进行定向蚀刻损伤。侧壁间隔物也可以在去除绝缘层之前通过蚀刻去除。

4. 发明授权

US06373091B1 Vertical DRAM cell with TFT over trench capacitor 有权
公开(公告)号：US06373091B1
公开(公告)日：2002-04-16
申请号：US09765561
申请日：2001-01-19
申请人： David Vaclav Horak , Rick Lawrence Mohler , Gorden Seth Starkey, Jr.
发明人： David Vaclav Horak , Rick Lawrence Mohler , Gorden Seth Starkey, Jr.
IPC分类号： H01L27108
摘要： A memory cell which comprises a substrate having a top surface; a capacitor extending vertically into the substrate for storing a voltage representing a datum, said capacitor occupying a geometrically shaped horizontal area; a transistor formed above the capacitor and occupying a horizontal area substantially equal to the geometrically shaped horizontal area, and having a vertical device depth, for establishing an electrical connection with the capacitor, in response to a control signal, for reading from, and writing to, the capacitor, wherein the transistor includes a gate formed near the periphery of said horizontal device area and having a vertical depth approximately equal to the vertical device depth; an oxide layer on an inside surface of the gate; a conductive body formed inside the oxide layer, said conductive body having a top surface and a bottom surface and a vertical depth approximately equal to the vertical device depth; and diffusion regions in the body near the top and bottom surfaces and a method of manufacturing the same is provided.

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