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1. 发明授权

US06693473B2 Delay lock loop having a variable voltage regulator 有权
标题翻译：具有可变电压调节器的延迟锁定环
公开(公告)号：US06693473B2
公开(公告)日：2004-02-17
申请号：US10100713
申请日：2002-03-19
申请人： George W. Alexander , Jinhwan Lee
发明人： George W. Alexander , Jinhwan Lee
IPC分类号： H03L706
CPC分类号： H03L7/0814
摘要： A delay lock loop circuit includes a forward delay circuit having a plurality of delay elements. Each delay element has a delay time of one unit delay time. The forward delay circuit and each of the delay elements are powered by a supply voltage. The supply voltage is set to thereby set the duration of a unit delay time. Moreover, a feedback delay circuit is provided in order to cause a feedback delay time being substantially equal to a propagation delay of the IC. As the operating conditions of IC change, and the propagation delay thereof increases or decreases, the feedback delay time changes accordingly, and thus the delay caused by forward delay circuit tracks the change in the propagation delay of the IC.
摘要翻译：延迟锁定环电路包括具有多个延迟元件的正向延迟电路。每个延迟元件具有一个单位延迟时间的延迟时间。正向延迟电路和每个延迟元件由电源电压供电。设定电源电压，从而设定单位延迟时间的持续时间。此外，提供反馈延迟电路以使得反馈延迟时间基本上等于IC的传播延迟。随着IC的工作条件变化，其传播延迟增大或减小，反馈延迟时间相应变化，因此由正向延迟电路引起的延迟跟踪IC传播延迟的变化。

2. 发明授权

US06653875B2 Method and apparatus for a delay lock loop 有权
标题翻译：延迟锁定环路的方法和装置
公开(公告)号：US06653875B2
公开(公告)日：2003-11-25
申请号：US10095318
申请日：2002-03-11
申请人： Torsten Partsch , George W. Alexander
发明人： Torsten Partsch , George W. Alexander
IPC分类号： H03L706
CPC分类号： H03L7/0802 , H03L7/0814 , H03L7/087
摘要： A delay lock loop circuit includes a forward delay circuit receiving a reference clock signal and issuing a delayed clock signal. The forward delay circuit adjustably shifts in time the delayed clock signal relative to the reference clock signal. An inverter receives the delayed clock signal and issues an inverted delayed clock signal. A feedback delay circuit receives a selected one of the delayed and the inverted delayed clock signals, and issues a feedback clock signal that is shifted in time relative to the selected one of the delayed and the inverted delayed clock signals. The feedback clock signal is compared to the reference clock signal. The time shift of the delayed clock signal is adjusted to thereby time-align the reference clock signal and the feedback clock signal.
摘要翻译：延迟锁定环电路包括接收参考时钟信号并发出延迟的时钟信号的正向延迟电路。正向延迟电路在时间上可调节延迟的时钟信号相对于参考时钟信号的移位。反相器接收延迟的时钟信号并发出反相延迟的时钟信号。反馈延迟电路接收延迟和反相延迟的时钟信号中选择的一个，并且发出相对于所选择的延迟和反相延迟时钟信号之一在时间上移位的反馈时钟信号。将反馈时钟信号与参考时钟信号进行比较。调整延迟时钟信号的时移，从而使参考时钟信号和反馈时钟信号进行时间对准。

3. 发明授权

US06516006B1 Self-adjusting clock phase controlled architecture 失效
标题翻译：自适应时钟相位控制架构
公开(公告)号：US06516006B1
公开(公告)日：2003-02-04
申请号：US09250161
申请日：1999-02-16
申请人： Robert M. Walker , Stephen M. Camacho , George W. Alexander
发明人： Robert M. Walker , Stephen M. Camacho , George W. Alexander
IPC分类号： H04J306
CPC分类号： G06F7/00 , G06F1/10 , H04L7/0008
摘要： A self-adjusting path is created by utilizing a phase detector and modifying a clock path and a data path to enable the passing of data in either phase of the clock. The new input path is controlled by the output of the phase detector. Each time a command is issued, the phase of the clock is detected and latched. The phase of the clock at the time the command issues is thus captured and can propagate through the pipeline along with the data. Accordingly, each stage along the data path can be synchronized to a different phase of the clock to reduce data corruption.
摘要翻译：通过使用相位检测器和修改时钟路径和数据路径来创建自调整路径，以使得能够在时钟的任一阶段中传送数据。新的输入路径由相位检测器的输出控制。每次发出命令时，检测并锁存时钟的相位。因此捕获命令发生时钟的时钟相位，并可以与数据一起通过流水线传播。因此，沿着数据路径的每个阶段可以被同步到时钟的不同阶段以减少数据损坏。

4. 发明授权

US06888365B2 Semiconductor wafer testing system 失效
标题翻译：半导体晶圆测试系统
公开(公告)号：US06888365B2
公开(公告)日：2005-05-03
申请号：US10242894
申请日：2002-09-12
申请人： Daivid Suitwai Ma , James J. Dietz , George W. Alexander
发明人： Daivid Suitwai Ma , James J. Dietz , George W. Alexander
IPC分类号： G01R31/317 , H01L23/58 , G01R31/02 , G01R31/26
CPC分类号： G01R31/318511 , G01R31/31724 , H01L22/32
摘要： A semiconductor wafer testing system tests one or more die clusters on a semiconductor wafer, using a test circuit to test multiple sections or areas of each die in parallel. The semiconductor wafer testing system has a buffer connected to the die cluster via the test circuit. The buffer writes test data onto a section of each die in the die cluster. The buffer reads test data from the section of each die in the die cluster.
摘要翻译：半导体晶片测试系统使用测试电路来测试半导体晶片上的一个或多个管芯簇，以平行地测试每个管芯的多个部分或区域。半导体晶片测试系统具有通过测试电路连接到芯片组的缓冲器。缓冲区将测试数据写入管芯集群中每个管芯的一部分。缓冲区从管芯集群中的每个管芯的部分读取测试数据。

5. 发明授权

US06845048B2 System and method for monitoring internal voltages on an integrated circuit 有权
标题翻译：用于监控集成电路内部电压的系统和方法
公开(公告)号：US06845048B2
公开(公告)日：2005-01-18
申请号：US10255767
申请日：2002-09-25
申请人： George W. Alexander , Jennifer F. Huckaby , Steven M. Baker , David S. Ma
发明人： George W. Alexander , Jennifer F. Huckaby , Steven M. Baker , David S. Ma
IPC分类号： G11C7/10 , G11C7/16 , G11C11/4096 , G11C11/4193 , G11C29/02 , G11C11/4074 , H03K17/693
CPC分类号： G11C29/021 , G11C7/1006 , G11C7/16 , G11C11/401 , G11C11/4096 , G11C29/02 , G11C2029/5004
摘要： A system and method for monitoring internal voltage sources in an integrated circuit, such as a DRAM integrated circuit, includes an internal analog multiplexing circuit, an internal analog-to-digital converter, and an interface circuit. Through the analog multiplexing circuit, the analog-to-digital converter sequentially connects to each voltage source and converts the measured voltage level of the source to a binary word. The interface circuit presents the binary word, e.g., serially, to test equipment off the integrated circuit.
摘要翻译：用于监视诸如DRAM集成电路的集成电路中的内部电压源的系统和方法包括内部模拟复用电路，内部模数转换器和接口电路。通过模拟多路复用电路，模数转换器顺序地连接到每个电压源，并将源的测量电压电平转换成二进制字。接口电路例如串行地呈现二进制字以从集成电路测试设备。

6. 发明授权

US06777990B2 Delay lock loop having an edge detector and fixed delay 有权
标题翻译：具有边缘检测器和固定延迟的延迟锁定环
公开(公告)号：US06777990B2
公开(公告)日：2004-08-17
申请号：US10100639
申请日：2002-03-19
申请人： Torsten Partsch , George W. Alexander
发明人： Torsten Partsch , George W. Alexander
IPC分类号： H03L706
CPC分类号： H03L7/0814 , H03L7/10
摘要： A delay lock loop circuit includes a forward delay circuit receiving a reference clock signal and issuing a first delayed clock signal. The forward delay circuit adjustably shifts in time the first delayed clock signal relative to the reference clock signal. A fixed delay circuit receives the first delayed clock signal and issues a second delayed clock signal. A feedback delay circuit receives a selected one of the first delayed and the second delayed clock signals, and issues a feedback clock signal. The feedback clock signal is shifted in time relative to the selected one of the first delayed and the second delayed clock signals.
摘要翻译：延迟锁定环电路包括接收参考时钟信号并发出第一延迟时钟信号的正向延迟电路。前向延迟电路相对于参考时钟信号可调节地调整第一延迟时钟信号的时间。固定延迟电路接收第一延迟时钟信号并且发出第二延迟时钟信号。反馈延迟电路接收所选择的第一延迟时钟信号和第二延迟时钟信号中的一个，并发出反馈时钟信号。所述反馈时钟信号相对于所述第一延迟时钟信号和所述第二延迟时钟信号中的所选择的时钟信号在时间上移位。

7. 发明授权

US06765419B2 Dynamic delay line control 有权
标题翻译：动态延时线控制
公开(公告)号：US06765419B2
公开(公告)日：2004-07-20
申请号：US10094793
申请日：2002-03-11
申请人： George W. Alexander
发明人： George W. Alexander
IPC分类号： H03L706
CPC分类号： H03L7/0802 , H03L7/0814
摘要： A delay lock loop circuit for aligning in time a reference clock signal with an internal feedback clock signal includes a forward delay circuit that receives the reference clock signal. The forward delay circuit includes a forward delay line having a plurality of electrically interconnected delay blocks. Each of the delay blocks includes a predetermined number of electrically interconnected delay units. Disabling means deactivate the one or more delay blocks when the delay blocks are not needed in order to time align the reference clock signal and the internal feedback clock signal.
摘要翻译：用于在时间上对准参考时钟信号和内部反馈时钟信号的延迟锁定环路包括接收参考时钟信号的前向延迟电路。前向延迟电路包括具有多个电互连延迟块的正向延迟线。每个延迟块包括预定数量的电互连延迟单元。当不需要延迟块以便时间对齐参考时钟信号和内部反馈时钟信号时，禁用意味着停用一个或多个延迟块。

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