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1. 发明授权

US06277682B1 Source drain implant process for mixed voltage CMOS devices 有权
标题翻译：用于混合电压CMOS器件的源极漏极注入工艺
公开(公告)号：US06277682B1
公开(公告)日：2001-08-21
申请号：US09382920
申请日：1999-08-25
申请人： George R. Misium
发明人： George R. Misium
IPC分类号： H01L218238
CPC分类号： H01L21/823814
摘要： A mixed voltage CMOS process for fabricating transistors with different source-drain profiles is described. The present invention comprises a method for manufacturing a CMOS integrated circuit with a low voltage device 24 and a high voltage device 26 comprising the steps of obtaining active regions in a substrate 10 with gates 30 and 32 for the low voltage device 24 and the high voltage device 26, respectively, obtaining lightly implanted source and drain extensions 38 and 40 for the low voltage device 24, forming a side wall 42, 44, 46 and 48 next to each gate 30 and 32, and angularly implanting each of the source and drain regions 52, 54, 56 and 58 with an impurity 50 of a selected type for both the low voltage device 24 and the high voltage device 26, to eliminate the need for separately implanting the first voltage device and second voltage device with different source-drain extensions. The method of the present invention tailors the source-drain implant conditions (energy, dose, angle 60, and thermal drive) to create the source-drain profiles of a reliable high voltage device 26 without degrading the performance of the low voltage device 24.
摘要翻译：描述了用于制造具有不同源极 - 漏极分布的晶体管的混合电压CMOS工艺。本发明包括一种用于制造具有低电压装置24和高电压装置26的CMOS集成电路的方法，包括以下步骤：在具有用于低电压装置24的门30和32的基板10中获得有源区，器件26分别获得用于低电压器件24的轻微植入的源极和漏极延伸部分38和40，形成在每个栅极30和32旁边的侧壁42,44,46和48，以及角度地植入源极和漏极区域52,54,56和58，其具有用于低电压装置24和高压装置26的所选类型的杂质50，以消除分别注入具有不同源极 - 漏极的第一电压装置和第二电压装置的需要扩展。本发明的方法调节源极 - 漏极注入条件（能量，剂量，角度60和热驱动）以产生可靠的高电压器件26的源极 - 漏极分布，而不降低低电压器件24的性能。

2. 发明授权

US06261973B1 Remote plasma nitridation to allow selectively etching of oxide 有权
标题翻译：远程等离子体氮化以允许选择性地蚀刻氧化物
公开(公告)号：US06261973B1
公开(公告)日：2001-07-17
申请号：US09215477
申请日：1998-12-18
申请人： George R. Misium , Sunil V. Hattangady
发明人： George R. Misium , Sunil V. Hattangady
IPC分类号： H01L21469
CPC分类号： H01L21/76224 , H01L21/31116 , H01L21/3144 , H01L21/823462
摘要： A method is disclosed of nitridating an oxide containing surface the disclosed method includes the steps of, obtaining a substrate, growing an oxide layer on the substrate, exposing the surface of the oxide layer to a nitrogen ion containing plasma at, e.g., room temperature, wherein the nitrogen ions form a nitrided layer on the oxide layer resistant to chemistries used to etch oxide.
摘要翻译：公开了一种对含氧化物表面进行氮化的方法，所述方法包括以下步骤：获得衬底，在衬底上生长氧化物层，将氧化物层的表面暴露于例如室温下含有等离子体的氮离子，其中所述氮离子在所述氧化物层上形成对用于蚀刻氧化物的化学物质有抗性的氮化层。

3. 发明授权

US06284599B1 Method to fabricate a semiconductor resistor in embedded flash memory application 有权
标题翻译：在嵌入式闪存应用中制造半导体电阻的方法
公开(公告)号：US06284599B1
公开(公告)日：2001-09-04
申请号：US09585059
申请日：2000-06-01
申请人： Freidoon Mehrad , George R. Misium , John H. MacPeak
发明人： Freidoon Mehrad , George R. Misium , John H. MacPeak
IPC分类号： H01L21336
CPC分类号： H01L27/115 , H01L27/0629 , H01L27/11521 , H01L27/11526 , H01L27/11531 , H01L28/20
摘要： A method for fabricating a semiconductor resistor in embedded FLASH memory applications is described. In the method a gate stack (54) is formed on an insulating region (70) of a semiconductor substrate. The control gate (20) is removed from the gate stack (54) and electric contacts (125), (130) are formed to contact the floating gate (16) to form the resistor.
摘要翻译：描述了在嵌入式FLASH存储器应用中制造半导体电阻器的方法。在该方法中，在半导体衬底的绝缘区域（70）上形成栅叠层（54）。控制栅极（20）从栅极堆叠（54）移除，并且电触点（125），（130）形成为接触浮动栅极（16）以形成电阻器。

4. 发明授权

US6140024A Remote plasma nitridation for contact etch stop 有权
标题翻译：远程等离子体氮化接触蚀刻停止
公开(公告)号：US6140024A
公开(公告)日：2000-10-31
申请号：US216145
申请日：1998-12-18
申请人： George R. Misium , Sunil V. Hattangady
发明人： George R. Misium , Sunil V. Hattangady
IPC分类号： H01L21/768 , G03C5/00
CPC分类号： H01L21/76832 , H01L21/76802 , H01L21/76826 , H01L21/76834
摘要： A method is disclosed of nitridating an oxide layer (12) to form a stop layer for selective etching of sacrificial layer comprising the steps of, obtaining a wafer (10), forming a gate (30) on the wafer (10), depositing an oxide layer (12) on the wafer (10) and the gate (30), exposing the surface of the oxide layer (12) to a nitrogen ion containing plasma at, e.g., room temperature, wherein the nitrogen ions form a nitrided layer (22) on the oxide layer (12). Next, a silicate layer (32) is deposited on the nitrided layer (22), planarized and patterned with photoresist (14) for etching. The contacts or vias are then formed through the silicate layer (32) by etching down to the nitrided layer (22) that acts as a stop layer, followed by a second etching step that removes the nitrided layer (22). The photoresist (14) is then stripped and the silicon oxide layer (12) etch down to the wafer (10). The process of the present invention prevents the exposure of the wafer (10) to contaminants from the photoresist layer (14) and the etch chemicals that can deposit reactive radicals. These reactive radicals, also known as mobile ions, decrease the reliability of the device by contaminating subsequent layers or structures.
摘要翻译：公开了一种氮化氧化物层（12）以形成用于选择性蚀刻牺牲层的停止层的方法，包括以下步骤：获得晶片（10），在晶片（10）上形成栅极（30），沉积在所述晶片（10）和所述栅极（30）上的氧化物层（12），将所述氧化物层（12）的表面暴露于例如室温的含有氮离子的等离子体，其中所述氮离子形成氮化层（ 22）在氧化物层（12）上。接着，将硅酸盐层（32）沉积在氮化层（22）上，用光致抗蚀剂（14）进行平坦化并图案化以进行蚀刻。然后通过蚀刻到作为停止层的氮化层（22），随后通过去除氮化层（22）的第二蚀刻步骤，通过硅酸盐层（32）形成触点或通孔。然后剥离光致抗蚀剂（14），并且氧化硅层（12）向下蚀刻到晶片（10）。本发明的方法防止晶片（10）暴露于光致抗蚀剂层（14）的污染物和可沉积反应性基团的蚀刻化学品。这些反应性基团，也称为移动离子，通过污染随后的层或结构而降低了器件的可靠性。

5. 发明授权

US5320934A Bilayer photolithographic process 失效
标题翻译：双层光刻工艺
公开(公告)号：US5320934A
公开(公告)日：1994-06-14
申请号：US26632
申请日：1993-03-05
申请人： George R. Misium , Charles B. Dobson
发明人： George R. Misium , Charles B. Dobson
IPC分类号： G03F7/095 , G03F7/40
CPC分类号： G03F7/095
摘要： In a process for creating a mask on the surface of an integrated circuit workpiece, a first layer of resist is applied to the surface of the workpiece. An upper portion of this first layer is metallized. A second layer of photoresist is applied to the first layer. The second layer of photoresist is selectively exposed and developed. Using the developed second layer as a mask, exposed respective areas of the metallized upper portion of the first layer are etched, and the non-metallized portions of the first layer are subsequently etched. The result is a metallized mask on the surface of the workpiece that avoids the problems of high topographical relief and irradiation reflections from the workpiece surface.
摘要翻译：在用于在集成电路工件的表面上形成掩模的工艺中，将第一层抗蚀剂施加到工件的表面。该第一层的上部被金属化。将第二层光致抗蚀剂施加到第一层。选择性地曝光和显影第二层光致抗蚀剂。使用显影的第二层作为掩模，蚀刻第一层的金属化上部的暴露的各个区域，并且随后蚀刻第一层的非金属化部分。结果是在工件表面上的金属化掩模，避免了来自工件表面的高形貌浮雕和照射反射的问题。

6. 发明授权

US06268296B1 Low temperature process for multiple voltage devices 有权
标题翻译：多电压器件的低温工艺
公开(公告)号：US06268296B1
公开(公告)日：2001-07-31
申请号：US09216562
申请日：1998-12-18
申请人： George R. Misium , Sunil V. Hattangady
发明人： George R. Misium , Sunil V. Hattangady
IPC分类号： H01L2131
CPC分类号： H01L21/823462 , H01L21/3143
摘要： A method is disclosed for making gate oxides on a silicon wafer surface for multiple voltage applications comprising the steps of growing an oxide layer (12) on a wafer (10) surface. Next, a photoresist layer (14) is deposited over a portion of the oxide layer (12) and the isolation (30). The entire wafer (10) is exposed to a nitrogen ion containing plasma to form a nitrided layer (22). The photoresist (14) is removed, and the exposed portion of the oxide layer (12) is etched to the wafer (10) surface. Finally, an oxidation step forms a silicon dioxide layer (34) having a different thickness than the silicon dioxide layer (12).
摘要翻译：公开了一种用于在硅晶片表面上制造用于多个电压应用的栅极氧化物的方法，包括在晶片（10）表面上生长氧化物层（12）的步骤。接下来，在氧化物层（12）和隔离层（30）的一部分上沉积光致抗蚀剂层（14）。将整个晶片（10）暴露于含有等离子体的氮离子以形成氮化层（22）。去除光致抗蚀剂（14），并将氧化物层（12）的暴露部分蚀刻到晶片（10）表面。最后，氧化步骤形成具有与二氧化硅层（12）不同的厚度的二氧化硅层（34）。

7. 发明授权

US6004871A Implant enhancement of titanium silicidation 失效
标题翻译：钛硅化物的植入物增强
公开(公告)号：US6004871A
公开(公告)日：1999-12-21
申请号：US868173
申请日：1997-06-03
申请人： Jorge Adrian Kittl , Keith A. Joyner , George R. Misium
发明人： Jorge Adrian Kittl , Keith A. Joyner , George R. Misium
IPC分类号： H01L21/285 , H01L21/265 , H01L21/28 , H01L21/324 , H01L21/336 , H01L29/78 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/28052 , H01L29/665
摘要： A method of forming silicided narrow (i.e., sub-0.25 .mu.m) polysilicon lines. A layer of titanium is deposited over a semiconductor body having polysilicon lines formed thereon Either before or after the titanium deposition and before the react step, an implant is performed using a gas that will not poison the subsequent silicidation reaction. Exemplary gases include the noble element gases such as argon, krypton, xenon, and neon. The titanium is then reacted with the polysilicon lines to form titanium silicide. The gas implant causes the C49 grain size of the titanium silicide to be reduced, which makes the transformation to the C54 phase easier. Finally, an anneal is performed to transform the titanium silicide from the C49 phase to the C54 phase.
摘要翻译：一种形成硅化窄（即0.25μm以下）多晶硅生产线的方法。一层钛沉积在其上形成有多晶硅线的半导体本体上。在钛沉积之前或之后，在反应步骤之前，使用不会中毒随后的硅化反应的气体进行植入。示例性气体包括贵金属气体，例如氩气，氪气，氙气和氖气。然后使钛与多晶硅线路反应形成硅化钛。气体注入导致硅化钛的C49晶粒尺寸减小，这使得转变为C54相变得更容易。最后，进行退火以将硅化钛从C49相转变为C54相。

8. 发明授权

US5970345A Method of forming an integrated circuit having both low voltage and high voltage MOS transistors 有权
标题翻译：形成具有低电压和高压MOS晶体管的集成电路的方法
公开(公告)号：US5970345A
公开(公告)日：1999-10-19
申请号：US177424
申请日：1998-10-22
申请人： Sunil V. Hattangady , George R. Misium
发明人： Sunil V. Hattangady , George R. Misium
IPC分类号： H01L21/8234 , H01L27/088 , H01L21/336
CPC分类号： H01L21/823462 , H01L27/088 , Y10S438/981
摘要： The invention comprises an integrated circuit having both low voltage and high voltage MOS transistors and a method for making the integrated circuit. In accordance with the method of making the integrated circuit, a first oxide layer is formed outwardly from a semiconductor substrate comprising a low voltage region and a high voltage region. A sacrificial layer is formed outwardly from the first oxide layer. The part of the sacrificial layer disposed outwardly from the low voltage region is removed to form an intermediate structure. The intermediate structure is selectively etched to remove the part of the first oxide layer disposed outwardly from the low voltage region. A second oxide layer is then formed comprising a first area disposed outwardly from the low voltage region and second area disposed outwardly from the high voltage region. The formation of the second oxide layer in the second area consumes the sacrificial layer.
摘要翻译：本发明包括具有低电压和高压MOS晶体管的集成电路以及用于制造集成电路的方法。根据制造集成电路的方法，从包括低电压区域和高电压区域的半导体衬底向外形成第一氧化物层。从第一氧化物层向外形成牺牲层。从低电压区域向外设置的牺牲层的部分被去除以形成中间结构。选择性地蚀刻中间结构以去除从低压区域向外设置的第一氧化物层的部分。然后形成第二氧化物层，其包括从低电压区域向外设置的第一区域和从高电压区域向外设置的第二区域。在第二区域中形成第二氧化物层消耗牺牲层。

9. 发明授权

US5753420A Rough dielectric film by etchback of residue 失效
标题翻译：粗糙的电介质膜通过回蚀残留物
公开(公告)号：US5753420A
公开(公告)日：1998-05-19
申请号：US713338
申请日：1996-09-13
申请人： George R. Misium
发明人： George R. Misium
IPC分类号： H01L27/04 , G03F7/00 , G03F7/09 , G03F7/16 , G03F7/26 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： G03F7/0035 , G03F7/094 , G03F7/168 , H01L28/92 , G03F7/265
摘要： A capacitor and method of forming the capacitor for high density applications. The capacitor (100) comprises a storage node (106) having peaks (108) formed on a surface thereof. The peaks (108) are created by forming a photoresist residue layer (130) on the polysilicon layer of the storage node (108). The structure is then dry etched using the residue layer (130) as a mask to create peaks (108).
摘要翻译：一种形成用于高密度应用的电容器的电容器和方法。电容器（100）包括在其表面上形成有峰（108）的存储节点（106）。通过在存储节点（108）的多晶硅层上形成光致抗蚀剂残留层（130）来形成峰（108）。然后使用残余层（130）作为掩模来干燥蚀刻该结构以产生峰（108）。

10. 发明授权

US06331492B2 Nitridation for split gate multiple voltage devices 有权
标题翻译：分闸门多电压装置的氮化
公开(公告)号：US06331492B2
公开(公告)日：2001-12-18
申请号：US09215909
申请日：1998-12-18
申请人： George R. Misium , Sunil V. Hattangady
发明人： George R. Misium , Sunil V. Hattangady
IPC分类号： H01L2131
CPC分类号： H01L21/76224 , H01L21/0214 , H01L21/0217 , H01L21/02332 , H01L21/0234 , H01L21/3105 , H01L21/3115 , H01L21/3143 , H01L21/31662 , H01L21/823462 , Y10S438/976 , Y10S438/981
摘要： A method is disclosed for making gate oxides on a silicon wafer surface for multiple voltage applications comprising the steps of growing an oxide layer (12) on a wafer (10) surface, exposing the surface of the oxide layer (12) to a nitrogen ion containing plasma to form a nitrided layer (22). Next, a photoresist layer (14) is deposited over a portion of the oxide layer (12) and the isolation (30), followed by etching of the exposed nitrided layer 22 and a portion of the oxide layer (12) to create a thinner silicon dioxide layer (32). The photoresist layer (14) is removed, the wafer (10) is cleaned and then the thinner silicon dioxide layer (32) is removed prior to a final oxidation step to form a thinner silicon dioxide layer (34) having a different thickness than the silicon dioxide layer (12).
摘要翻译：公开了一种用于在多个电压应用的硅晶片表面上制造栅极氧化物的方法，包括以下步骤：在晶片（10）表面上生长氧化物层（12），将氧化物层（12）的表面暴露于氮离子含有等离子体以形成氮化层（22）。接下来，在氧化物层（12）和隔离层（30）的一部分上沉积光致抗蚀剂层（14），然后蚀刻暴露的氮化层22和一部分氧化物层（12）以产生更薄的二氧化硅层（32）。去除光致抗蚀剂层（14），清洁晶片（10），然后在最终氧化步骤之前去除较薄的二氧化硅层（32），以形成具有不同厚度的二氧化硅层（34）二氧化硅层（12）。

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