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1. 发明授权

US07042765B2 Memory bit line segment isolation 有权
标题翻译：内存位线隔离
公开(公告)号：US07042765B2
公开(公告)日：2006-05-09
申请号：US10912824
申请日：2004-08-06
申请人： James M. Sibigtroth , George L. Espinor , Bruce L. Morton
发明人： James M. Sibigtroth , George L. Espinor , Bruce L. Morton
IPC分类号： G11C16/04
CPC分类号： G11C7/18 , G11C7/12 , G11C16/06 , G11C16/24 , G11C2207/005 , G11C2216/22
摘要： A single memory array (10) has an isolation circuit for isolating segments of a same bit line (Seg1 BL0, Seg2 BL0) from each other. The isolation circuit (16) permits memory cells located in one segment (12) of an array to be read while memory cells of another segment (14) of the array are being erased. In one example, the isolation circuit (16) electrically couples the segments during a read or program of memory cells located on the second segment (Seg2 BL0). Program information stored in the single memory array may always be accessed while a portion of the same array is erased. Dynamic variation of the size of the isolated bit line segment occurs when multiple isolation circuits are used to create more than two array segments.
摘要翻译：单个存储器阵列（10）具有用于隔离相同位线（Seg1BL0，Seg2BL0）的段的隔离电路。隔离电路（16）允许位于阵列的一个段（12）中的存储器单元被读取，同时阵列的另一段（14）的存储单元被擦除。在一个示例中，隔离电路（16）在位于第二段（Seg 2 BL 0）上的存储单元的读取或编程期间电耦合该段。存储在单个存储器阵列中的程序信息可以总是被访问，而同一阵列的一部分被擦除。当使用多个隔离电路创建两个以上的阵列段时，发生隔离位线段的大小的动态变化。

2. 发明授权

US07187600B2 Method and apparatus for protecting an integrated circuit from erroneous operation 有权
标题翻译：用于保护集成电路免于错误操作的方法和装置
公开(公告)号：US07187600B2
公开(公告)日：2007-03-06
申请号：US10946951
申请日：2004-09-22
申请人： James M. Sibigtroth , George L. Espinor , Bruce L. Morton , Michael C. Wood
发明人： James M. Sibigtroth , George L. Espinor , Bruce L. Morton , Michael C. Wood
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G11C5/145 , G11C7/24 , G11C16/12 , G11C2207/104
摘要： A data processing system (10) has an embedded non-volatile memory (22) that is programmed and erased by use of a high voltage provided by a charge pump (78). In order to prevent the non-volatile memory (22) from being inadvertently programmed or erased during low power supply voltage conditions, the charge pump (78) is disabled and discharged when the power supply voltage drops below a predetermined value. This is accomplished by enabling a low voltage detect circuit (110) in response to a program or erase operation being initiated. A control register (76) will provide a high voltage enable signal to the charge pump (78) only when a power supply valid signal is received. In another embodiment, the low voltage detect circuit (110) may be enabled by another condition to protect the data processing system (10) from an authorized access.
摘要翻译：数据处理系统（10）具有通过使用由电荷泵（78）提供的高电压来编程和擦除的嵌入式非易失性存储器（22）。为了防止在低电源电压条件期间非易失性存储器（22）被无意地编程或擦除，当电源电压降低到预定值以下时，电荷泵（78）被禁用和放电。这是通过响应于开始的编程或擦除操作启用低电压检测电路（110）来实现的。仅当接收到电源有效信号时，控制寄存器（76）将向电荷泵（78）提供高电压使能信号。在另一个实施例中，低电压检测电路（110）可以被另一条件启用，以保护数据处理系统（10）免受授权访问。

3. 发明授权

US5890191A Method and apparatus for providing erasing and programming protection for electrically erasable programmable read only memory 失效
标题翻译：为电可擦除可编程只读存储器提供擦除和编程保护的方法和装置
公开(公告)号：US5890191A
公开(公告)日：1999-03-30
申请号：US644098
申请日：1996-05-10
申请人： George L. Espinor , Michael I. Catherwood
发明人： George L. Espinor , Michael I. Catherwood
IPC分类号： G11C16/02 , G11C7/24 , G11C16/06 , G11C16/22 , G06F12/16 , G11C16/04
CPC分类号： G11C7/24 , G11C16/22
摘要： Method and apparatus for providing erasing and programming protection of an EEPROM (22) to significantly reduce the possibility of unintentional erasing or programming of the EEPROM (22). In one embodiment, a read access of a block protect value (111) is a requirement for enabling the EEPROM charge pump (78). The block protect value (111) may be located in the EEPROM array (22) itself. In one embodiment, an externally provided signal (24) must be provided to an integrated circuit (10) in order to enable a write access to modify the block protect value (111). In one embodiment, a charge pump enable value (103) is provided to enable or disable operation of the charge pump (78). Thus, a combination of hardware and software protection is provided for an EEPROM (22), including protection for enabling of a charge pump (78).
摘要翻译：用于提供EEPROM（22）的擦除和编程保护以显着减少EEPROM（22）的无意擦除或编程的可能性的方法和装置。在一个实施例中，块保护值（111）的读取访问是启用EEPROM电荷泵（78）的要求。块保护值（111）可以位于EEPROM阵列（22）本身中。在一个实施例中，必须向集成电路（10）提供外部提供的信号（24），以便能够进行写访问以修改块保护值（111）。在一个实施例中，提供电荷泵使能值（103）以使能或禁止电荷泵（78）的运行。因此，为EEPROM（22）提供硬件和软件保护的组合，包括用于启用电荷泵（78）的保护。

4. 发明授权

US07293188B2 Low voltage detection system 有权
标题翻译：低电压检测系统
公开(公告)号：US07293188B2
公开(公告)日：2007-11-06
申请号：US10292323
申请日：2002-11-12
申请人： George L. Espinor , William L. Lucas , Michael C. Wood
发明人： George L. Espinor , William L. Lucas , Michael C. Wood
IPC分类号： G06F1/28
CPC分类号： G06F1/3203 , G06F1/28 , G06F1/30
摘要： A low voltage detection (LVD) system for a logic device includes a first LVD circuit (110) to provide an indicator when a supply pin voltage (109) falls below a first voltage level, and a second LVD circuit (116) to provide an interrupt (118) when the supply pin voltage falls below a second voltage level. In one embodiment, the second LVD circuit consumes more power than the first LVD circuit, and is therefore selectively enabled. In one embodiment, when the supply pin voltage is between the first and second voltage levels and the logic device is in a stop or low power mode, the second LVD circuit is periodically enabled to monitor the supply pin voltage. After the supply pin voltage falls below the second voltage level, the logic device is placed in a safe state where the logic device is inhibited from acknowledging interrupts until the supply pin voltage rises above the first voltage level.
摘要翻译：用于逻辑器件的低电压检测（LVD）系统包括第一LVD电路（110），用于当电源引脚电压（109）低于第一电压电平时提供指示器;以及第二LVD电路（116）当电源引脚电压低于第二电压电平时，中断（118）。在一个实施例中，第二LVD电路比第一LVD电路消耗更多的功率，因此被选择性地使能。在一个实施例中，当电源引脚电压处于第一和第二电压电平之间并且逻辑器件处于停止或低功率模式时，周期性地使第二LVD电路监视电源引脚电压。在电源引脚电压低于第二电压电平之后，逻辑器件处于安全状态，在该状态下，禁止逻辑器件确认中断，直到电源引脚电压升高到高于第一电压电平。

5. 发明授权

US5706228A Method for operating a memory array 失效
标题翻译：操作存储器阵列的方法
公开(公告)号：US5706228A
公开(公告)日：1998-01-06
申请号：US603939
申请日：1996-02-20
申请人： Kuo-Tung Chang , Craig A. Cavins , Ko-Min Chang , Bruce L. Morton , George L. Espinor
发明人： Kuo-Tung Chang , Craig A. Cavins , Ko-Min Chang , Bruce L. Morton , George L. Espinor
IPC分类号： G11C16/04 , G11C16/10 , G11C11/40
CPC分类号： G11C16/3427 , G11C16/0433 , G11C16/10
摘要： A memory array (25) having a selected memory cell (10) and an unselected memory cell (30) is programmed and read. Each memory cell in the memory array (25) contains an isolation transistor (22) and a floating gate transistor (23). To program the selected memory cell (10), programming voltages are applied to a control gate line (21), a drain line (14), an isolation line (19), and a source line (12). To reduce the effects of the drain disturb problem, a gate terminal (32) of the unselected memory cell (30) is held at a positive voltage. To read selected memory cell (10), a read voltage is applied to an isolation gate line (31) of unselected memory cell (30) which insures that the unselected memory cell (30) does not conduct or contribute to leakage current and power consumption during the read operation.
摘要翻译：具有选定的存储单元（10）和未选择的存储单元（30）的存储器阵列（25）被编程和读取。存储器阵列（25）中的每个存储单元包含隔离晶体管（22）和浮动栅极晶体管（23）。为了对所选择的存储单元（10）进行编程，将编程电压施加到控制栅极线（21），漏极线（14），隔离线（19）和源极线（12）。为了减小漏极干扰问题的影响，未选择的存储单元（30）的栅极端子（32）被保持在正电压。为了读取所选择的存储单元（10），读取电压被施加到未选择存储单元（30）的隔离栅极线（31），其确保未选择的存储单元（30）不导通或有助于漏电流和功耗在读操作期间。

6. 发明授权

US5598569A Data processor having operating modes selected by at least one mask option bit and method therefor 失效
标题翻译：具有由至少一个掩码选项位选择的操作模式的数据处理器及其方法
公开(公告)号：US5598569A
公开(公告)日：1997-01-28
申请号：US323558
申请日：1994-10-17
申请人： Michael I. Catherwood , George L. Espinor
发明人： Michael I. Catherwood , George L. Espinor
IPC分类号： G11C5/00 , G11C16/20 , G06F12/16
CPC分类号： G06F9/30079 , G11C16/20
摘要： A data processor (20) includes a nonvolatile memory system (25) which stores not only normal program memory (31), but also mask option bits (32), within a common array (30) of nonvolatile memory cells. A control circuit (40) of the nonvolatile memory system (25) detects when a central processing unit (21) is accessing the program memory (31). In response to either an end of reset signal or a refresh request signal, the control circuit (40) copies the mask option bits (32) into a volatile mask option register (44) only when the central processing unit (21) is not accessing the program memory (31). Otherwise, the control circuit (40) holds off the access to the mask option bits (32). The mask option register (44) provides signals to various circuits (28) to control their operation. Thus, the mask option bits (32) may be stored in nonvolatile form in the same array (30) as the program memory (31), enhancing reliability and reducing integrated circuit size.
摘要翻译：数据处理器（20）包括非易失性存储器系统（25），其在非易失性存储器单元的公共阵列（30）内不仅存储正常程序存储器（31），而且存储掩模选项位（32）。非易失性存储器系统（25）的控制电路（40）检测中央处理单元（21）何时正在访问程序存储器（31）。响应于复位信号的结束或刷新请求信号，仅当中央处理单元（21）不访问时，控制电路（40）将掩模选项位（32）复制到易失性掩模选项寄存器（44）程序存储器（31）。否则，控制电路（40）停止对掩模选项位（32）的访问。掩模选项寄存器（44）向各种电路（28）提供信号以控制其操作。因此，掩模选项位（32）可以以与程序存储器（31）相同的阵列（30）以非易失性形式存储，增强了可靠性并降低了集成电路尺寸。

7. 发明授权

US4802119A Single chip microcomputer with patching and configuration controlled by on-board non-volatile memory 失效
标题翻译：单片机具有由板载非易失性存储器控制的修补和配置
公开(公告)号：US4802119A
公开(公告)日：1989-01-31
申请号：US026511
申请日：1987-03-17
申请人： Mark R. Heene , Michael H. Menkedick , James M. Sibigtroth , George L. Espinor
发明人： Mark R. Heene , Michael H. Menkedick , James M. Sibigtroth , George L. Espinor
IPC分类号： G06F9/26 , G06F9/445 , G06F15/78 , G06F9/00
CPC分类号： G06F9/328 , G06F15/7814 , G06F8/66
摘要： A single chip microcomputer with patching and configuration is provided with blocks of patch memory which may be patched over faulty and/or obsolete areas of the microcomputer's memory map under control of starting address registers which are implemented in on-board non-volatile memory. The starting address registers, and enable registers which control whether each patch block is placed in the memory map, are programmable under control of the microcomputer's CPU. Newly programmed values in these registers are not effective to alter the memory map until a reset sequence enables a latch. In particular embodiments, patch blocks may overlie mask ROM, internal EPROM and/or EEPROM, external memory or devices or any other desireable portion of the memory map.
摘要翻译：具有修补和配置的单片微计算机具有块补丁存储器块，其可以在实现在板载非易失性存储器中的起始地址寄存器的控制下在微机存储器映射的故障和/或过时区域进行修补。启动地址寄存器和控制每个补丁块是否置于存储器映射中的使能寄存器都可以在微机CPU的控制下进行编程。这些寄存器中的新编程值在重置序列启用锁存器之前，无法更改存储器映射。在特定实施例中，贴片块可以覆盖掩模ROM，内部EPROM和/或EEPROM，外部存储器或设备或存储器映射的任何其它可望的部分。

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