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1. 发明申请

US20130007667A1 PEOPLE CENTRIC, CROSS SERVICE, CONTENT DISCOVERY SYSTEM 审中-公开
标题翻译：人民中心，交叉服务，内容发现系统
公开(公告)号：US20130007667A1
公开(公告)日：2013-01-03
申请号：US13170293
申请日：2011-06-28
申请人： Aaron Sauve , Jannes Paul Peters , Marc David McClure , Kathryn Lemson , Divya Tyamagundlu , Ian Middleton , Sushil Kumar , Peter Bohac , Aravind Narayanan Manimandiram , Gary Daniels , Jonathan Gass
发明人： Aaron Sauve , Jannes Paul Peters , Marc David McClure , Kathryn Lemson , Divya Tyamagundlu , Ian Middleton , Sushil Kumar , Peter Bohac , Aravind Narayanan Manimandiram , Gary Daniels , Jonathan Gass
IPC分类号： G06F3/048
CPC分类号： G06F16/54
摘要： A menu structure is provided which allows a user of a computing device to more easily consolidate and navigate images and/or albums regardless of their location. Moreover, the menu structure is dynamically tailored to individual users based on their previous interactions with the people appearing in the images/albums. The menu includes icons representing images (e.g., photos) or collections of images that have been categorized based in part on metadata respectively associated with the images. The metadata may have been provided by tagging the images or posting the images on one or more social networking sites. The order in which the icons are presented on the menu or interface may be based on their relative relevance or importance to the user.
摘要翻译：提供了一种菜单结构，其允许计算设备的用户更容易地整合和导航图像和/或相册，而不管其位置如何。此外，菜单结构根据他们以前与图像/专辑中出现的人的交互动态地针对个人用户进行动态定制。该菜单包括表示图像的图标（例如，照片）或已经基于分别与图像相关联的元数据分类的图像集合。可以通过标记图像或在一个或多个社交网站上发布图像来提供元数据。在菜单或界面上呈现图标的顺序可以基于它们对用户的相对关联性或重要性。

2. 发明授权

US4409671A Data processor having single clock pin 失效
标题翻译：数据处理器具有单个时钟引脚
公开(公告)号：US4409671A
公开(公告)日：1983-10-11
申请号：US295912
申请日：1981-08-24
申请人： R. Gary Daniels , Thomas H. Bennett , Fuad H. Musa , Michael F. Wiles
发明人： R. Gary Daniels , Thomas H. Bennett , Fuad H. Musa , Michael F. Wiles
IPC分类号： G06F1/06 , G06F1/04
CPC分类号： G06F1/06
摘要： A microprocessor on a monolithic integrated circuit is provided having a single clock input pin for receiving a clock input signal. The clock input signal is used to gate address data onto the address bus and to enable a data input dynamic latch. In addition the input clock signal is used to generate two complementary non-overlapping clock signals used for synchronizing purposes within the microprocessor.
摘要翻译：提供了具有用于接收时钟输入信号的单个时钟输入引脚的单片集成电路上的微处理器。时钟输入信号用于将地址数据输入到地址总线上，并使数据输入动态锁存。此外，输入时钟信号用于产生用于微处理器内的同步目的的两个互补非重叠时钟信号。

3. 发明授权

US4266270A Microprocessor having plural internal data buses 失效
标题翻译：具有多个内部数据总线的微处理器
公开(公告)号：US4266270A
公开(公告)日：1981-05-05
申请号：US939741
申请日：1978-09-05
申请人： R. Gary Daniels , Fuad H. Musa , William B. Wilder, Jr. , Michael F. Wiles , Thomas H. Bennett
发明人： R. Gary Daniels , Fuad H. Musa , William B. Wilder, Jr. , Michael F. Wiles , Thomas H. Bennett
IPC分类号： G06F7/00 , G06F9/30 , G06F15/78 , G06F1/00
CPC分类号： G06F15/7832
摘要： A microprocessor comprises an internal address bus having a first portion (2,4) having a plurality of conductors carrying the low order address byte and a second portion (10) having a plurality of conductors for carrying the high order address byte. The microprocessor further comprises a plurality of registers, including an incrementor (12,13), a program counter (14,15), a temporary register (16,17), a stack pointer (18,19), an index register (20,21), and an accumulator (22,24), each comprising a pair of 8-bit registers for temporarily storing information. An arithmetic logic unit (28) performs computational operations on digital information within the microprocessor. The microprocessor includes a pair of internal data buses (6,8) each having a plurality of conductors for conducting digital information within the microprocessor. Means are provided for coupling selected ones of the registers, or the high or low order portions thereof, to the first and second data buses. The provision plural internal data buses permits a greater number of transfers of digital information to occur within the microprocessor during each machine cycle. The result is more efficient microprocessor operation and higher throughput.
摘要翻译：微处理器包括具有第一部分（2,4）的内部地址总线，第一部分（2,4）具有承载低阶地址字节的多个导体，以及具有用于承载高位地址字节的多个导体的第二部分（10）。微处理器还包括多个寄存器，包括一个增量器（12,13），一个程序计数器（14,15），一个临时寄存器（16,17），堆栈指针（18,19），索引寄存器，21）和累加器（22,24），每个包括用于临时存储信息的一对8位寄存器。算术逻辑单元（28）对微处理器内的数字信息进行计算操作。微处理器包括一对内部数据总线（6,8），每个内部数据总线具有用于在微处理器内进行数字信息的多个导体。提供了用于将所选择的一个寄存器或其高阶或低阶部分耦合到第一和第二数据总线的装置。提供多个内部数据总线允许在每个机器周期期间在微处理器内发生更多数量的数字信息传送。结果是更高效的微处理器操作和更高的吞吐量。

4. 发明授权

US4330842A Valid memory address pin elimination 失效
标题翻译：有效的内存地址引脚消除
公开(公告)号：US4330842A
公开(公告)日：1982-05-18
申请号：US939723
申请日：1978-09-05
申请人： R. Gary Daniels , Thomas H. Bennett , Michael F. Wiles
发明人： R. Gary Daniels , Thomas H. Bennett , Michael F. Wiles
IPC分类号： G06F1/22 , G06F13/42 , G06F3/00 , G06F13/00
CPC分类号： G06F1/22 , G06F13/4243
摘要： A digital data processor on a single monolithic integrated circuit chip is provided which uses one less pin. The elimination of the pin is accomplished by using, internally to the processor, a valid memory address signal to gate information from the address but to an address output line. Whenever an address is not present on the address bus all logic "1's" are generated on the address output bus.
摘要翻译：提供了单个单片集成电路芯片上的数字数据处理器，其使用少一个引脚。通过在处理器内部使用有效的存储器地址信号到从地址到地址输出线的门信息来实现引脚的消除。每当地址总线上不存在地址时，地址输出总线上都会产生逻辑“1”。

5. 发明授权

US3943699A Ultra thin electronic watch 失效
标题翻译：超薄电子手表
公开(公告)号：US3943699A
公开(公告)日：1976-03-16
申请号：US540370
申请日：1975-01-13
申请人： R. Gary Daniels
发明人： R. Gary Daniels
IPC分类号： G04G9/00 , G04G17/02 , G04C3/00
CPC分类号： G04G17/02 , G04G9/0035
摘要： The thickness of an electronic watch body may be substantially reduced by having portions of the top surface of the watch extend above the remainder of the top surface. Components of the watch which otherwise result in requiring a thick watch body, such as the battery or the display element (e.g., a liquid crystal display), project up into these raised portions.
摘要翻译：电子表体的厚度可以通过使手表顶表面的部分在顶表面的其余部分上方延伸而大大减小。否则导致需要诸如电池或显示元件（例如液晶显示器）的厚表壳主体的手表的部件突出到这些凸起部分中。

6. 发明授权

US4203157A Carry anticipator circuit and method 失效
标题翻译：携带预测电路和方法
公开(公告)号：US4203157A
公开(公告)日：1980-05-13
申请号：US939724
申请日：1978-09-05
申请人： R. Gary Daniels , Fuad H. Musa , W. Bryant Wilder, Jr. , Michael F. Wiles , Thomas H. Bennett
发明人： R. Gary Daniels , Fuad H. Musa , W. Bryant Wilder, Jr. , Michael F. Wiles , Thomas H. Bennett
IPC分类号： G06F9/22 , G06F7/50 , G06F7/506 , G06F7/507 , G06F9/30 , G06F9/32 , G06F15/78
CPC分类号： G06F7/506 , G06F9/321 , G06F9/322 , G06F9/324
摘要： A circuit and a method for adding an 8-bit operand to a 16-bit operand are disclosed such that the number of machine cycles required by a data processor to perform such an addition is reduced. The 8-bit operand and the least significant byte of the 16-bit operand are added together within an 8-bit adder circuit to generate the least significant byte of the result. Simultaneously, the most significant byte of the 16-bit operand is stored in a temporary register and is also input to an increment/decrement network. The adder circuit, after a given delay time, generates a carry signal depending on whether a carry-out was produced by the addition. The carry signal and the sign bit of the 8-bit operand control the mode of operation of the increment/decrement network and determine whether the increment/decrement network or the temporary register will be selected to provide the most significant byte of the result.
摘要翻译：公开了一种用于将8位操作数添加到16位操作数的电路和方法，使得数据处理器执行这种添加所需的机器周期数减少。 8位操作数和16位操作数的最低有效字节在8位加法器电路中相加在一起，以生成结果的最低有效字节。同时，16位操作数的最高有效字节存储在临时寄存器中，并且也被输入到递增/递减网络。在给定的延迟时间之后，加法器电路根据加法产生进位是否产生进位信号。 8位操作数的进位信号和符号位控制增量/减量网络的运行模式，并确定增量/减量网络或临时寄存器是否被选择以提供结果的最高有效字节。

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