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1. 发明授权

US09389275B2 Techniques for calibrating measurement systems 有权
标题翻译：校准测量系统的技术
公开(公告)号：US09389275B2
公开(公告)日：2016-07-12
申请号：US13362208
申请日：2012-01-31
申请人： Gabriel Banarie , Andreas Callanan , Damien McCartney , Colin Lyden
发明人： Gabriel Banarie , Andreas Callanan , Damien McCartney , Colin Lyden
IPC分类号： G01R35/00 , G01R31/319
CPC分类号： G01R31/3191
摘要： Techniques to provide calibration of a measurement system in conjunction with measurement operations. The techniques may include providing a reference device in a signal processing chain within the measurement system. An excitation signal may be driven through the reference device while it may be connected to the signal processing chain within the measurement system and a calibration response may be captured. During a measurement operation, the reference device connection may be complemented with a sensor connection in the signal processing chain and the excitation signal may be driven through the signal processing chain. A measurement response may be captured from the system. The measurement system may generate a calibrated measurement signal that accounts for phase and/or amplitude errors within the system from the calibration response and the measurement response.
摘要翻译：与测量操作一起提供测量系统校准的技术。这些技术可以包括在测量系统内的信号处理链中提供参考装置。激励信号可以通过参考装置驱动，同时其可以连接到测量系统内的信号处理链，并且可以捕获校准响应。在测量操作期间，参考设备连接可以与信号处理链中的传感器连接互补，激励信号可以通过信号处理链驱动。可以从系统捕获测量响应。测量系统可以产生校准的测量信号，其根据校准响应和测量响应考虑系统内的相位和/或幅度误差。

2. 发明申请

US20060213270A1 One terminal capacitor interface circuit 有权
标题翻译：一个端子电容接口电路
公开(公告)号：US20060213270A1
公开(公告)日：2006-09-28
申请号：US11370764
申请日：2006-03-08
申请人： John O'Dowd , Damien McCartney , Gabriel Banarie
发明人： John O'Dowd , Damien McCartney , Gabriel Banarie
IPC分类号： G01P15/125
CPC分类号： G01D5/24 , G01P15/125 , H03M3/34 , H03M3/458
摘要： A one terminal capacitor interface circuit for sensing the capacitance of a capacitor includes a differential integrating amplifier having an input common mode voltage and two summing nodes whose voltage is substantially equal to the input common mode voltage, a switching circuit for charging the capacitor to a first voltage level in a first phase, connecting, in a second phase, the capacitor to one of the summing nodes of the differential amplifier to provide a first output change substantially representative of the difference between the first voltage level and the input common mode voltage, and also representative of the capacitor; charging the capacitor to a second voltage level in a third phase, and connecting, in a fourth phase, the capacitor to the other summing node of the differential amplifier to provide a second output change substantially representative of the difference between the second voltage level and the input common mode voltage, and also representative of the capacitor; the combined first and second output changes representing the capacitance of the capacitor substantially independent of the input common mode voltage.
摘要翻译：用于感测电容器的电容的单端电容器接口电路包括具有输入共模电压的差分积分放大器和电压基本上等于输入共模电压的两个求和节点，用于将电容器充电到第一电压电平在第一阶段中，在第二阶段将电容器连接到差分放大器的求和节点之一，以提供基本上代表第一电压电平和输入共模电压之间的差的第一输出变化，以及也代表电容器; 在第三相中将电容器充电到第二电压电平，并且在第四相中将电容器连接到差分放大器的另一个求和节点，以提供基本上代表第二电压电平与第二电压电平之间的差的第二输出变化输入共模电压，也代表电容; 组合的第一和第二输出变化表示电容器的电容基本上独立于输入共模电压。

3. 发明授权

US09124290B2 Method and apparatus for separating the reference current from the input signal in sigma-delta converter 有权
标题翻译：用于在Σ-Δ转换器中分离参考电流与输入信号的方法和装置
公开(公告)号：US09124290B2
公开(公告)日：2015-09-01
申请号：US13757455
申请日：2013-02-01
申请人： Adrian W. Sherry , Gabriel Banarie , Roberto S. Maurino
发明人： Adrian W. Sherry , Gabriel Banarie , Roberto S. Maurino
IPC分类号： H03M3/00 , G06G7/184
CPC分类号： H03M3/30 , G06G7/184 , H03M3/322 , H03M3/358 , H03M3/458 , H03M3/496
摘要： An integrator system may have a pair of sampling circuits each having a sampling capacitor to sample a respective component of a differential input signal, and an integrator having inputs coupled to outputs of the sampling circuits. The system may have a shorting switch coupled between input terminals of the sampling capacitors. The shorting switch may be engaged during an interstitial phase between sampling and output phases of the sampling circuits. By shorting input terminals of the sampling capacitors together, the design reduces current drawn by the system and, in some designs, severs relationships between current draw and information content sampled by the system. The integrator system may receive analog and digital input signals.
摘要翻译：积分器系统可以具有一对采样电路，每个采样电路各自具有采样电容器以对差分输入信号的相应分量进行采样，以及具有耦合到采样电路的输出的输入的积分器。该系统可以具有耦合在采样电容器的输入端之间的短路开关。在采样电路的采样和输出阶段之间的间隙阶段，短路开关可能被接合。通过将采样电容器的输入端子短路在一起，该设计减少了系统吸收的电流，并且在一些设计中，切断了电流抽取与系统采样的信息内容之间的关系。积分器系统可以接收模拟和数字输入信号。

4. 发明授权

US08653996B2 Stability correction for a shuffler of a Σ-delta ADC 有权
标题翻译： Sigma-Delta ADC的洗牌机的稳定性校正
公开(公告)号：US08653996B2
公开(公告)日：2014-02-18
申请号：US13685063
申请日：2012-11-26
申请人： Gabriel Banarie , Adrian Sherry
发明人： Gabriel Banarie , Adrian Sherry
IPC分类号： H03M3/00
CPC分类号： H03M3/30 , H03M1/00 , H03M1/0668 , H03M1/66 , H03M1/74 , H03M3/464
摘要： A sigma-delta analog-to-digital converter (“ΣΔ ADC”) may include a loop filter, ADC, a feedback digital-to-analog converter (“DAC”), and a control circuit. The feedback DAC may include several unit elements (resistors, capacitors, or current sources) that, ideally, are identical to each other but vary due to mismatch errors introduced during manufacture. Mismatch errors may introduce signal errors that generate undesirable noise frequencies and non-linearities in a ΣΔ ADC output signal. Embodiments of the present invention provide a stability corrected second order shuffler that allows for the shaping of the frequency response by the ΣΔ ADC to reduce the effect of the mismatch error between DAC unit elements. The second order shuffler may include accumulation correctors, to suppress saturation for accumulators within the shuffler. The suppression may compress the range of accumulation values for each accumulator while maintaining context for the values to stabilize operation of the second order shuffler.
摘要翻译： Σ-Δ模数转换器（“SigmaDelta ADC”）可以包括环路滤波器，ADC，反馈数模转换器（“DAC”）和控制电路。反馈DAC可以包括理想地彼此相同但由于在制造期间引入的失配错误而变化的几个单元元件（电阻器，电容器或电流源）。不匹配误差可能引入在SigmaDelta ADC输出信号中产生不良噪声频率和非线性的信号误差。本发明的实施例提供了稳定性校正的二阶洗牌器，其允许通过SigmaDelta ADC对频率响应进行整形，以减少DAC单元元件之间的失配误差的影响。第二级洗牌器可以包括累积校正器，以抑制洗牌器内的累加器的饱和。抑制可以压缩每个累加器的累加值的范围，同时保持值的上下文以稳定二阶洗牌器的操作。

5. 发明申请

US20130193982A1 TECHNIQUES FOR CALIBRATING MEASUREMENT SYSTEMS 有权
标题翻译：用于校准测量系统的技术
公开(公告)号：US20130193982A1
公开(公告)日：2013-08-01
申请号：US13362208
申请日：2012-01-31
申请人： Gabriel Banarie , Andreas Callanan , Damien McCartney , Colin Lyden
发明人： Gabriel Banarie , Andreas Callanan , Damien McCartney , Colin Lyden
IPC分类号： G01R35/00
CPC分类号： G01R31/3191
摘要： Techniques to provide calibration of a measurement system in conjunction with measurement operations. The techniques may include providing a reference device in a signal processing chain within the measurement system. An excitation signal may be driven through the reference device while it may be connected to the signal processing chain within the measurement system and a calibration response may be captured. During a measurement operation, the reference device connection may be complemented with a sensor connection in the signal processing chain and the excitation signal may be driven through the signal processing chain. A measurement response may be captured from the system. The measurement system may generate a calibrated measurement signal that accounts for phase and/or amplitude errors within the system from the calibration response and the measurement response.
摘要翻译：与测量操作一起提供测量系统校准的技术。这些技术可以包括在测量系统内的信号处理链中提供参考装置。激励信号可以通过参考装置驱动，同时其可以连接到测量系统内的信号处理链，并且可以捕获校准响应。在测量操作期间，参考设备连接可以与信号处理链中的传感器连接互补，激励信号可以通过信号处理链驱动。可以从系统捕获测量响应。测量系统可以产生校准的测量信号，其根据校准响应和测量响应考虑系统内的相位和/或幅度误差。

6. 发明申请

US20150323950A1 VOLTAGE REFERENCE CIRCUIT 有权
标题翻译：电压参考电路
公开(公告)号：US20150323950A1
公开(公告)日：2015-11-12
申请号：US14272061
申请日：2014-05-07
申请人： Stefan MARINCA , Gabriel BANARIE
发明人： Stefan MARINCA , Gabriel BANARIE
IPC分类号： G05F3/16
CPC分类号： G05F3/30 , G05F3/16
摘要： The present disclosure relates to a method and apparatus for generating a voltage reference. More particularly the present disclosure relates to a methodology and circuitry configured to provide an output signal that combines a proportional to absolute temperature component with a complimentary to absolute temperature component to generate a stable output which is not temperature dependent.
摘要翻译：本公开涉及一种用于产生电压参考的方法和装置。更具体地说，本公开涉及一种被配置为提供将比例绝对温度分量与绝对温度分量组合的输出信号的方法和电路，以产生不依赖于温度的稳定输出。

7. 发明申请

US20130207821A1 METHOD AND APPARATUS FOR SEPARATING THE REFERENCE CURRENT FROM THE INPUT SIGNAL IN SIGMA-DELTA CONVERTER 有权
标题翻译：用于分离SIGMA-DELTA转换器中的输入信号的参考电流的方法和装置
公开(公告)号：US20130207821A1
公开(公告)日：2013-08-15
申请号：US13757455
申请日：2013-02-01
申请人： Adrian W. SHERRY , Gabriel BANARIE , Roberto S. MAURINO
发明人： Adrian W. SHERRY , Gabriel BANARIE , Roberto S. MAURINO
IPC分类号： H03M3/00
CPC分类号： H03M3/30 , G06G7/184 , H03M3/322 , H03M3/358 , H03M3/458 , H03M3/496
摘要： An integrator system may have a pair of sampling circuits each having a sampling capacitor to sample a respective component of a differential input signal, and an integrator having inputs coupled to outputs of the sampling circuits. The system may have a shorting switch coupled between input terminals of the sampling capacitors. The shorting switch may be engaged during an interstitial phase between sampling and output phases of the sampling circuits. By shorting input terminals of the sampling capacitors together, the design reduces current drawn by the system and, in some designs, severs relationships between current draw and information content sampled by the system. Configurations are disclosed for analog and digital input signals.
摘要翻译：积分器系统可以具有一对采样电路，每个采样电路各自具有采样电容器以对差分输入信号的相应分量进行采样，以及具有耦合到采样电路的输出的输入的积分器。该系统可以具有耦合在采样电容器的输入端之间的短路开关。在采样电路的采样和输出阶段之间的间隙阶段，短路开关可能被接合。通过将采样电容器的输入端子短路在一起，该设计减少了系统吸收的电流，并且在一些设计中，切断了电流抽取与系统采样的信息内容之间的关系。公开了用于模拟和数字输入信号的配置。

8. 发明申请

US20130207819A1 STABILITY CORRECTION FOR A SHUFFLER OF A SIGMA-DELTA ADC 有权
标题翻译：用于SIGMA-DELTA ADC的稳压器的稳定性校正
公开(公告)号：US20130207819A1
公开(公告)日：2013-08-15
申请号：US13685063
申请日：2012-11-26
申请人： Gabriel BANARIE , Adrian SHERRY
发明人： Gabriel BANARIE , Adrian SHERRY
IPC分类号： H03M3/00 , H03M1/00 , H03M1/66
CPC分类号： H03M3/30 , H03M1/00 , H03M1/0668 , H03M1/66 , H03M1/74 , H03M3/464
摘要： A sigma-delta analog-to-digital converter (“ΣΔ ADC”) may include a loop filter, ADC, a feedback digital-to-analog converter (“DAC”), and a control circuit. The feedback DAC may include several unit elements (resistors, capacitors, or current sources) that, ideally, are identical to each other but vary due to mismatch errors introduced during manufacture. Mismatch errors may introduce signal errors that generate undesirable noise frequencies and non-linearities in a ΣΔ ADC output signal. Embodiments of the present invention provide a stability corrected second order shuffler that allows for the shaping of the frequency response by the ΣΔ ADC to reduce the effect of the mismatch error between DAC unit elements. The second order shuffler may include accumulation correctors, to suppress saturation for accumulators within the shuffler. The suppression may compress the range of accumulation values for each accumulator while maintaining context for the values to stabilize operation of the second order shuffler.
摘要翻译： Σ-Δ模数转换器（“SigmaDelta ADC”）可以包括环路滤波器，ADC，反馈数模转换器（“DAC”）和控制电路。反馈DAC可以包括理想地彼此相同但由于在制造期间引入的失配错误而变化的几个单元元件（电阻器，电容器或电流源）。不匹配误差可能引入在SigmaDelta ADC输出信号中产生不良噪声频率和非线性的信号误差。本发明的实施例提供了稳定性校正的二阶洗牌器，其允许通过SigmaDelta ADC对频率响应进行整形，以减少DAC单元元件之间的失配误差的影响。第二级洗牌器可以包括累积校正器，以抑制洗牌器内的累加器的饱和。抑制可以压缩每个累加器的累加值的范围，同时保持值的上下文以稳定二阶洗牌器的操作。

9. 发明授权

US07304483B2 One terminal capacitor interface circuit 有权
公开(公告)号：US07304483B2
公开(公告)日：2007-12-04
申请号：US11821746
申请日：2007-06-25
申请人： John O'Dowd , Damien McCartney , Gabriel Banarie
发明人： John O'Dowd , Damien McCartney , Gabriel Banarie
IPC分类号： G01R27/26 , H03M3/00
CPC分类号： G01D5/24 , G01P15/125 , H03M3/34 , H03M3/458
摘要： A differential capacitor one terminal capacitor interface circuit for sensing the capacitance of first and second capacitors includes a differential integrating amplifier having first and second summing nodes and an input common mode voltage; and a switching circuit for charging a first capacitor of said differential one terminal capacitor to a first voltage level and a second capacitor of said differential one terminal capacitor to a second voltage level in a first phase, in a second phase connecting said first capacitor to said first summing node and said second capacitor to said second summing node of said amplifier to provide first and second output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, in a third phase charging said first capacitor to said second voltage level and said second capacitor to said first voltage level, and in a fourth phase connecting said first capacitor to said second summing node and said second capacitor to said first summing node of said amplifier to provide third and fourth output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, the combined first, second, third and fourth changes representing the capacitance of said first and second capacitors substantially independent of said input common mode voltage.

10. 发明申请

US20070247171A1 One terminal capacitor interface circuit 有权
标题翻译：一个端子电容接口电路
公开(公告)号：US20070247171A1
公开(公告)日：2007-10-25
申请号：US11821746
申请日：2007-06-25
申请人： John O'Dowd , Damien McCartney , Gabriel Banarie
发明人： John O'Dowd , Damien McCartney , Gabriel Banarie
IPC分类号： G01R27/26
CPC分类号： G01D5/24 , G01P15/125 , H03M3/34 , H03M3/458
摘要： A differential capacitor one terminal capacitor interface circuit for sensing the capacitance of first and second capacitors includes a differential integrating amplifier having first and second summing nodes and an input common mode voltage; and a switching circuit for charging a first capacitor of said differential one terminal capacitor to a first voltage level and a second capacitor of said differential one terminal capacitor to a second voltage level in a first phase, in a second phase connecting said first capacitor to said first summing node and said second capacitor to said second summing node of said amplifier to provide first and second output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, in a third phase charging said first capacitor to said second voltage level and said second capacitor to said first voltage level, and in a fourth phase connecting said first capacitor to said second summing node and said second capacitor to said first summing node of said amplifier to provide third and fourth output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, the combined first, second, third and fourth changes representing the capacitance of said first and second capacitors substantially independent of said input common mode voltage.
摘要翻译：用于感测第一和第二电容器的电容的差分电容器一端电容器接口电路包括具有第一和第二求和节点和输入共模电压的差分积分放大器; 以及切换电路，用于将所述差分一端电容器的第一电容器充电到所述差分一端电容器的第一电容器和所述差分一端电容器的第二电容器到第一相位的第二电压电平，所述第二相位将所述第一电容器连接到所述第一求和节点和所述第二电容器到所述放大器的所述第二求和节点，以在第三阶段提供基本上代表所述第一和第二电压电平与所述输入共模电压之间的差的第一和第二输出变化，所述第二电压电平和所述第二电容器达到所述第一电压电平，并且在将所述第一电容器与所述第二求和节点和所述第二电容器连接到所述放大器的所述第一求和节点的第四阶段中，以提供基本上代表所述第一和第二电压电平与所述输入共模之间的差电压，组合的第一，第二，第三和第四变化表示所述第一和第二电容器的电容基本上独立于所述输入共模电压。

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