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1. 发明授权

US08882956B2 Composite structures using interpenetrating polymer network adhesives 有权
标题翻译：使用互穿聚合物网络粘合剂的复合结构
公开(公告)号：US08882956B2
公开(公告)日：2014-11-11
申请号：US12873537
申请日：2010-09-01
申请人： Gary Robert Weber
发明人： Gary Robert Weber
IPC分类号： B29C65/14 , B29C65/52 , C08F283/06 , C08F283/10
CPC分类号： C08J5/042 , B29C65/1403 , B29C65/1406 , B29C65/4835 , B29C65/4845 , B29C65/485 , B29C66/1122 , B29C66/45 , B29C66/71 , B29C66/721 , B29C66/7212 , B29C66/72141 , B29C66/73112 , B29C66/742 , C08J2335/02 , C08J2363/00 , C08L35/02 , C08L63/00 , C08L63/10 , C08L2205/04 , C09J5/06 , C09J135/02 , C09J163/00 , C09J2400/163 , C09J2463/00 , Y10T428/31515 , B29K2307/04 , B29K2309/08 , B29K2277/10 , B29K2063/00 , B29K2033/08 , B29K2031/00
摘要： An interpenetrating polymer network (IPN) adhesive comprises an acrylated polymer system curable by radiation, and a flexible epoxy system thermally curable after the acrylated polymer system is cured.
摘要翻译：互穿聚合物网络（IPN）粘合剂包括通过辐射固化的丙烯酸酯化聚合物体系，以及在丙烯酸酯化聚合物体系固化后可热固化的柔性环氧体系。

2. 发明申请

US20120052305A1 COMPOSITE STRUCTURES USING INTERPENETRATING POLYMER NETWORK ADHESIVES 有权
标题翻译：使用互聚聚合物网络粘合剂的复合结构
公开(公告)号：US20120052305A1
公开(公告)日：2012-03-01
申请号：US12873537
申请日：2010-09-01
申请人： GARY ROBERT WEBER
发明人： GARY ROBERT WEBER
IPC分类号： B32B27/38 , B29C65/14 , C08L63/00
CPC分类号： C08J5/042 , B29C65/1403 , B29C65/1406 , B29C65/4835 , B29C65/4845 , B29C65/485 , B29C66/1122 , B29C66/45 , B29C66/71 , B29C66/721 , B29C66/7212 , B29C66/72141 , B29C66/73112 , B29C66/742 , C08J2335/02 , C08J2363/00 , C08L35/02 , C08L63/00 , C08L63/10 , C08L2205/04 , C09J5/06 , C09J135/02 , C09J163/00 , C09J2400/163 , C09J2463/00 , Y10T428/31515 , B29K2307/04 , B29K2309/08 , B29K2277/10 , B29K2063/00 , B29K2033/08 , B29K2031/00
摘要： An interpenetrating polymer network (IPN) adhesive comprises an acrylated polymer system curable by radiation, and a flexible epoxy system thermally curable after the acrylated polymer system is cured.
摘要翻译：互穿聚合物网络（IPN）粘合剂包括通过辐射固化的丙烯酸酯化聚合物体系，以及在丙烯酸酯化聚合物体系固化后可热固化的柔性环氧体系。

3. 发明授权

US06197641B1 Process for fabricating vertical transistors 有权
标题翻译：制造垂直晶体管的工艺
公开(公告)号：US06197641B1
公开(公告)日：2001-03-06
申请号：US09335707
申请日：1999-06-18
申请人： John Michael Hergenrother , Donald Paul Monroe , Gary Robert Weber
发明人： John Michael Hergenrother , Donald Paul Monroe , Gary Robert Weber
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L29/161 , H01L29/7827 , H01L29/78642
摘要： A process for fabricating a vertical MOSFET device for use in integrated circuits is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET. In the process the first and third layers have etch rates that are significantly lower than the etch rate of the second layer in an etchant selected to remove the second layer. The top layer, which is either the third or subsequent layer, is a stop layer for a subsequently performed mechanical polishing step that is used to remove materials formed over the at least three layers. After the at least three layers of material are formed on the substrate, a window or trench is formed in the layers. The window terminates at the surface of the silicon substrate in which one of either a source or drain region is formed in the silicon substrate. The window or trench is then filled with a semiconductor material. This semiconductor plug becomes the vertical channel of the transistor. Therefore the crystalline semiconductor plug is doped to form a source extension, a drain extension, and a channel region in the plug. Subsequent processing forms the other of a source or drain on top of the vertical channel and removes the sacrificial second material layer. The removal of the sacrificial second layer exposes a portion of the doped semiconductor plug. The device gate dielectric is then formed on the exposed portion of the doped semiconductor plug. The gate electrode is then deposited. The physical gate length of the resulting device corresponds to the deposited thickness of the second material layer.
摘要翻译：公开了用于制造用于集成电路的垂直MOSFET器件的工艺。在该过程中，在半导体衬底上依次形成至少三层材料。三层被布置成使得第二层介于第一层和第三层之间。第二层是牺牲性的，即在随后的处理期间该层被完全去除。第二层的厚度限定了垂直MOSFET的物理栅极长度。在该过程中，第一层和第三层的蚀刻速率明显低于蚀刻剂中被选择去除第二层的第二层的蚀刻速率。顶层，其是第三层或后续层，是用于随后执行的机械抛光步骤的停止层，其用于去除在至少三层上形成的材料。在衬底上形成至少三层材料之后，在这些层中形成窗口或沟槽。窗口终止于在硅衬底中形成源区或漏区之一的硅衬底的表面。然后用半导体材料填充窗口或沟槽。该半导体插头成为晶体管的垂直沟道。因此，晶体半导体插头被掺杂以在插头中形成源延伸部，漏极延伸部和沟道区域。随后的处理形成垂直通道顶部的源极或漏极中的另一个，并去除牺牲的第二材料层。牺牲第二层的去除暴露了掺杂半导体插件的一部分。然后在掺杂半导体插头的暴露部分上形成器件栅极电介质。然后沉积栅电极。所得装置的物理栅极长度对应于第二材料层的沉积厚度。

4. 发明授权

US5985493A Membrane mask for projection lithography 失效
标题翻译：用于投影光刻的膜面罩
公开(公告)号：US5985493A
公开(公告)日：1999-11-16
申请号：US57420
申请日：1998-04-08
申请人： James Alexander Liddle , Anthony Edward Novembre , Gary Robert Weber
发明人： James Alexander Liddle , Anthony Edward Novembre , Gary Robert Weber
IPC分类号： H01L21/027 , G03F1/20 , G03F9/00
CPC分类号： G03F1/20
摘要： An improved, scattering-type mask for use in a charged-particle beam lithography process comprises the mask having a membrane portion and a scattering portion, the membrane portion being fabricated with a conductive material or a plurality of materials in which one of them is conductive. The conductive nature of the membrane portion mitigates the accumulation of charge in the mask, thereby enhancing the definition of the charged-particle pattern transferred from the mask onto the wafer under fabrication and reducing the distortion obtained with the system.
摘要翻译：用于带电粒子束光刻工艺的改进的散射型掩模包括具有膜部分和散射部分的掩模，膜部分由导电材料或多个材料制成，其中一个导电。膜部分的导电性质减轻了掩模中电荷的积累，从而增强了在制造过程中从掩模转移到晶片上的带电粒子图案的定义，并减少了用系统获得的失真。

5. 发明授权

US06240199B1 Electronic apparatus having improved scratch and mechanical resistance 失效
标题翻译：具有改进的划痕和机械阻力的电子设备
公开(公告)号：US06240199B1
公开(公告)日：2001-05-29
申请号：US08899735
申请日：1997-07-24
申请人： Lalita Manchanda , Edward Paul Martin, Jr. , Gary Robert Weber
发明人： Lalita Manchanda , Edward Paul Martin, Jr. , Gary Robert Weber
IPC分类号： G06K900
CPC分类号： G06K9/00053 , G01D5/24 , H01L23/562 , H01L2924/0002 , Y10T428/26 , H01L2924/00
摘要： Embodiments of the invention include a sensor such as a capacitive sensor with improved scratch resistance. The sensor has a substrate and a layer of sensing elements formed thereon that are formed from materials having a greater mechanical firmness than conventional aluminum or other soft metal materials. Sensor interconnects also are made of such materials. The increased mechanical firmness of the sensing elements and interconnects improves the scratch and mechanical resistance thereof by reducing scratches, mechanical stress and cracks by reducing the deformation and consequently the bridge and/or gap effects of the sensing element material. Such effects plague conventional electronic devices, integrated circuits and sensors. Alternatively, the inventive sensor includes, e.g., a dielectric region operably coupled to the sensing elements and interconnects, thus forming a capacitive sensor or other electronic devices. The sensing elements and interconnects are formed beneath, within or on top of the dielectric region, and their improved mechanical firmness improves the scratch and mechanical resistance of the dielectric region or other material region formed thereon.
摘要翻译：本发明的实施例包括诸如具有改进的耐擦伤性的电容式传感器的传感器。传感器具有形成在其上的基底和感应元件层，其由具有比常规铝或其它软金属材料更大的机械硬度的材料形成。传感器互连也由这样的材料制成。通过减小感应元件材料的变形和桥接和/或间隙效应，传感元件和互连件的增加的机械硬度通过减少划痕，机械应力和裂纹来改善其划痕和机械阻力。这种影响瘟疫常规电子设备，集成电路和传感器。或者，本发明的传感器包括例如可操作地耦合到感测元件和互连的电介质区域，从而形成电容式传感器或其它电子设备。感测元件和互连件形成在电介质区域的下方，内部或之上，并且它们改进的机械坚固性改善了形成在其上的电介质区域或其他材料区域的划痕和机械阻力。

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