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1. 发明授权

US07154978B2 Cascaded delay locked loop circuit 有权
标题翻译：级联延迟锁定环路
公开(公告)号：US07154978B2
公开(公告)日：2006-12-26
申请号：US10000914
申请日：2001-11-02
申请人： Jui-Kuo Juan , Robert E. Stengel , Frederick J. Martin , David E. Bockelman
发明人： Jui-Kuo Juan , Robert E. Stengel , Frederick J. Martin , David E. Bockelman
IPC分类号： H03D3/24
CPC分类号： H03L7/16 , H03L7/07 , H03L7/0812 , H03L7/14 , H03L2207/08
摘要： A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 . . . 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 . . . 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.
摘要翻译：在几个实施例中，延迟锁定环频率合成器使用主延迟线元件（24）和一个或多个辅助延迟元件（162 ... 164,270,310）。在一个实施例中，主延迟线（24）用于粗略地选择频率输出，而使用无源或有源的辅助延迟元件（162 ... 164,270,310）来增加初级延迟线（24）。在被动实施例中，通过从主延迟线（24）的输出抽头中选择分量作为被动次级延迟元件（310）的驱动信号来提供粗调和选择输出，可以进行粗略和精细的频率选择从第二延迟元件（310）提供精细选择。

2. 发明授权

US06690748B2 Receiver with improved digital intermediate to base band demodulator 有权
标题翻译：接收机具有改进的数字中频到基带解调器
公开(公告)号：US06690748B2
公开(公告)日：2004-02-10
申请号：US10036620
申请日：2001-12-21
申请人： Frederick J. Martin
发明人： Frederick J. Martin
IPC分类号： H04L2714
CPC分类号： H04L27/2332 , H03M3/40 , H03M3/462
摘要： A digital IF to base band demodulator (120) includes delta sigma samplers (202, 204) for sampling two channels of an IF signal at a sampling rate that is substantially higher than the Nyquist rate for the IF signal. A first pair of decimation filters (206, 208) decimates and filters the output of the delta sigma samplers (202, 204) but keeps the samples at a rate sufficient to perform digital mixing, cross adding, and pulse shape match filtering. A set of mixers (210, 212, 214, 216) mixers the output of the first pair of decimation filters with two phases of a digital representation of an local IF signal. A pair of summers (222, 224) sums, and subtracts outputs of the set of mixers (210, 212, 214, 216) in order to cancel undesired harmonics. A second set of decimation filters (226, 228) decimates and filters the output of the summers (222, 224) applying a filter function that is matched to a pulse shape of a base band signal present in the IF signal.
摘要翻译：数字IF到基带解调器（120）包括用于以基本上高于IF信号的奈奎斯特速率的采样速率对两个信道IF信号进行采样的Σ-Σ采样器（202,204）。第一对抽取滤波器（206,208）对Δ西格玛采样器（202,204）的输出进行抽取和滤波，但是将采样保持在足以执行数字混合，交叉加法和脉冲形状匹配滤波的速率。一组混频器（210,212,214,216）将第一对抽取滤波器的输出与本地IF信号的数字表示的两个相位进行混频。一对加法器（222,224）相加并减去该组混频器（210,212,214,216）的输出，以便消除不需要的谐波。第二组抽取滤波器（226,228）对施加与IF信号中存在的基带信号的脉冲形状匹配的滤波器函数的求和器（222,224）的输出进行抽选和滤波。

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