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1. 发明申请

US20050234692A1 Logic design modeling and interconnection 有权
标题翻译：逻辑设计建模与互连
公开(公告)号：US20050234692A1
公开(公告)日：2005-10-20
申请号：US10824489
申请日：2004-04-15
申请人： Frederic Reblewski
发明人： Frederic Reblewski
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A dynamic reconfigurable interconnect network architecture in a logic simulation system that interconnects a plurality of simulation engines together, providing a high degree of interconnectivity in an efficient manner. The logic simulation system may create and manage linkable sub-programs for execution by a simulation engine. The logic simulation system may schedule various tasks in a design to be simulated, including horizontal and vertical partitioning of the design and determination of an order in which events such as clock edges and asynchronous signals are to be implemented by a logic simulation system.
摘要翻译：在逻辑仿真系统中的动态可重配置互连网络架构，其将多个模拟引擎相互连接在一起，以有效的方式提供高度的互连性。逻辑仿真系统可以创建和管理可链接的子程序以供仿真引擎执行。逻辑仿真系统可以在要仿真的设计中调度各种任务，包括设计的水平和垂直划分以及由逻辑模拟系统实现时钟边缘和异步信号等事件的顺序的确定。

2. 发明授权

US06874136B2 Crossbar device with reduced parasitic capacitive loading and usage of crossbar devices in reconfigurable circuits 有权
标题翻译：具有降低的寄生电容负载和可重构电路中交叉开关器件的使用的交叉开关器件
公开(公告)号：US06874136B2
公开(公告)日：2005-03-29
申请号：US10043964
申请日：2002-01-10
申请人： Frederic Reblewski , Olivier Lepape
发明人： Frederic Reblewski , Olivier Lepape
IPC分类号： H03K17/16 , H03K17/693 , G06F17/50 , G06F9/45
CPC分类号： H03K17/693 , H03K17/162
摘要： A crossbar device includes a first set of input lines and a second set of output lines. A plurality of chains of pass transistors are provided to selectively couple the input lines to the output lines in a reduced parasitic capacitive loading manner. Further, memory elements and decoder logic are provided to facilitate control of the selective coupling. Additionally, a low power application of multiple crossbar devices to a reconfigurable circuit block is improved by having each memory element of a crossbar device be provided with a supply voltage higher by a Vth to maintain the input voltage of corresponding output buffers at Vdd. Further, an application of multiple crossbar devices to a reconfigurable circuit block is improved by coupling a control circuitry via a control line to all output buffers of the interconnected crossbar devices to force the output buffers to a known state at power-on.
摘要翻译：横杆装置包括第一组输入线和第二组输出线。提供多个传送晶体管链，以便以减小的寄生电容负载方式选择性地将输入线耦合到输出线。此外，提供存储器元件和解码器逻辑以便于选择性耦合的控制。此外，通过使交叉开关器件的每个存储器元件具有高于Vth的电源电压以将相应的输出缓冲器的输入电压维持在Vdd来提高多个交叉开关器件对可重构电路块的低功率应用。此外，通过经由控制线将控制电路耦合到互连的交叉开关器件的所有输出缓冲器来将多个交叉开关器件应用于可重新配置的电路块得到改善，以在上电时迫使输出缓冲器处于已知状态。

3. 发明授权

US06647362B1 Emulation system scaling 有权
标题翻译：仿真系统缩放
公开(公告)号：US06647362B1
公开(公告)日：2003-11-11
申请号：US09405602
申请日：1999-09-24
申请人： Frederic Reblewski , Jean Barbier , Olivier Lepape
发明人： Frederic Reblewski , Jean Barbier , Olivier Lepape
IPC分类号： G06F9455
CPC分类号： G06F17/5027
摘要： A scalable emulation system is disclosed. The basic embodiment of the emulation system includes a number of logic boards with logic chips that are reconfigurable to emulate circuit elements of a circuit design. The basic embodiment further includes a number of interconnect boards coupled to at least the logic boards. Each of the interconnect boards includes interconnect chips that are reconfigurable to selectively interconnect the logic chips of different ones of the logic boards. Additionally, at least each of a subset of the interconnect boards includes a number of expansion connectors for facilitating expansion of the emulation system in one or more selected ones of expansion orientations through coupling of at least one or more substantial replicates of the basic embodiment.
摘要翻译：公开了一种可扩展的仿真系统。仿真系统的基本实施例包括具有逻辑芯片的多个逻辑板，其可重构以仿真电路设计的电路元件。基本实施例还包括耦合到至少逻辑板的多个互连板。每个互连板包括互连芯片，其可重新配置以选择性地互连不同逻辑板的逻辑芯片。此外，互连板的子集中的至少每一个包括多个扩展连接器，用于通过耦合基本实施例的至少一个或多个基本重复来促进仿真系统在一个或多个选定扩展方向中的扩展。

4. 发明授权

US6057706A Field programmable gate array with integrated debugging facilities 失效
标题翻译：具有集成调试功能的现场可编程门阵列
公开(公告)号：US6057706A
公开(公告)日：2000-05-02
申请号：US985372
申请日：1997-12-04
申请人： Jean Barbier , Olivier LePape , Frederic Reblewski
发明人： Jean Barbier , Olivier LePape , Frederic Reblewski
IPC分类号： G01R31/317 , H03K19/177
CPC分类号： G01R31/31705 , G01R31/318519 , G01R31/318544 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17748 , H03K19/17764 , H03K19/17772
摘要： A number of enhanced logic elements (LEs) are provided to form a FPGA. Each enhanced LE comprises a multiple input-single output truth table, and a complementary pair of master-slave latches having a data, a set and a reset input. Each enhanced LE further comprises a plurality of multiplexers and buffers, and control logic. Additionally, the improved FPGA further comprises a network of crossbars, a context bus, a scan register, and a plurality of trigger circuitry. As a result, each LE may be individually initialized, its signal state frozen momentarily, the frozen state be read, trace data be output, and trigger inputs be conditionally generated. Furthermore, the enhanced LEs may be used for "level sensitive" as well as "edge sensitive" circuit design emulations.
摘要翻译：提供了许多增强型逻辑元件（LE）来形成FPGA。每个增强LE包括多输入单输出真值表，以及具有数据，集合和复位输入的互补对主控从锁存器。每个增强型LE还包括多个复用器和缓冲器以及控制逻辑。此外，改进的FPGA还包括交叉开关网络，上下文总线，扫描寄存器和多个触发电路。结果，每个LE可以被单独初始化，其信号状态暂时冻结，冻结状态被读取，跟踪数据被输出，并且有条件地产生触发输入。此外，增强型LE可用于“电平敏感”以及“边缘敏感”电路设计仿真。

5. 发明授权

US08003906B2 Crossbar device constructed with MEMS switches 有权
标题翻译：采用MEMS开关构成的横杆装置
公开(公告)号：US08003906B2
公开(公告)日：2011-08-23
申请号：US12263223
申请日：2008-10-31
申请人： Carl Ebeling , Frederic Reblewski , Olivier V. Lepape , Jean Barbier
发明人： Carl Ebeling , Frederic Reblewski , Olivier V. Lepape , Jean Barbier
IPC分类号： H01H57/00
CPC分类号： H01H59/0009
摘要： Embodiments of crossbar devices constructed with Micro-Electro-Mechanical Systems (MEMS) switches are disclosed herein. A crossbar device may comprise m input terminals, n output terminals, n control lines and m×n MEMS switches coupled to the n control lines to selectively couple the m input terminals to the n output terminal. Each of the MEMS switches may comprise a contact node coupled to one of the m input terminals, a cantilever coupled to one of the n output terminals, a control node coupled to one of the n control lines to electrostatically control the cantilever to contact the contact node or be away from the contact node using electrostatic attractive or repulsive force respectively. The cantilever and the contact node are configured to remain in contact by molecular adhesion force, after the cantilever has been electrostatically controlled to contact the contact node, and the electrostatic attractive force has been removed. Other embodiments may be described and claimed.
摘要翻译：本文公开了利用微机电系统（MEMS）开关构成的横杆装置的实施例。交叉开关装置可以包括m个输入端子，n个输出端子，n个控制线和耦合到n个控制线的m×n个MEMS开关，以将m个输入端子选择性地耦合到n个输出端子。每个MEMS开关可以包括耦合到m个输入端之一的接触节点，耦合到n个输出端中的一个的悬臂，耦合到n个控制线中的一个的控制节点，以静电控制悬臂以接触触点或者分别使用静电吸引力或排斥力离开接触节点。在悬臂被静电控制以接触接触节点之后，悬臂和接触节点构造成通过分子粘附力保持接触，并且静电吸引力已被去除。可以描述和要求保护其他实施例。

6. 发明授权

US07698118B2 Logic design modeling and interconnection 有权
标题翻译：逻辑设计建模与互连
公开(公告)号：US07698118B2
公开(公告)日：2010-04-13
申请号：US10824489
申请日：2004-04-15
申请人： Frederic Reblewski
发明人： Frederic Reblewski
IPC分类号： G06F17/50 , H03K17/693 , H03K19/00 , H03K19/173 , H03K19/177
CPC分类号： G06F17/5022
摘要： A dynamic reconfigurable interconnect network architecture in a logic simulation system that interconnects a plurality of simulation engines together, providing a high degree of interconnectivity in an efficient manner. The logic simulation system may create and manage linkable sub-programs for execution by a simulation engine. The logic simulation system may schedule various tasks in a design to be simulated, including horizontal and vertical partitioning of the design and determination of an order in which events such as clock edges and asynchronous signals are to be implemented by a logic simulation system.
摘要翻译：在逻辑仿真系统中的动态可重配置互连网络架构，其将多个模拟引擎相互连接在一起，以有效的方式提供高度的互连性。逻辑仿真系统可以创建和管理可链接的子程序以供仿真引擎执行。逻辑仿真系统可以在要仿真的设计中调度各种任务，包括设计的水平和垂直划分以及由逻辑模拟系统实现时钟边缘和异步信号等事件的顺序的确定。

7. 发明申请

US20070283190A1 RUNTIME RECONFIGURATION OF RECONFIGURABLE CIRCUITS 有权
标题翻译：可再生电路的运行重新配置
公开(公告)号：US20070283190A1
公开(公告)日：2007-12-06
申请号：US11840853
申请日：2007-08-17
申请人： Frederic Reblewski
发明人： Frederic Reblewski
IPC分类号： G06F11/00
CPC分类号： G11C29/12 , G01R31/31707 , G06F11/27 , G11C29/72 , G11C2029/0409 , H03K19/17764
摘要： A reconfigurable circuit having primary function blocks with runtime built-in self-test (BIST) circuitry, one or more redundant function blocks and runtime reconfiguration logic is described herein.
摘要翻译：具有运行时内置自检（BIST）电路的主要功能块，一个或多个冗余功能块和运行时重新配置逻辑的可重构电路在此被描述。

8. 发明申请

US20070162247A1 ON CIRCUIT FINALIZATION OF CONFIGURATION DATA IN A RECONFIGURABLE CIRCUIT 有权
标题翻译：在可重构电路中配置数据的电路振荡
公开(公告)号：US20070162247A1
公开(公告)日：2007-07-12
申请号：US11330418
申请日：2006-01-10
申请人： Frederic Reblewski
发明人： Frederic Reblewski
IPC分类号： G01R31/00 , G01R27/28
CPC分类号： G06F17/5054
摘要： Reconfigurable circuits with configuration data loaders are described herein. The configuration data loaders are adapted to enable on circuit finalization of configuration data provided in symbolic form, not fully resolved.
摘要翻译：这里描述了具有配置数据加载器的可重构电路。配置数据加载器适用于使得能够以符号形式提供的配置数据的电路完成，而不是完全解决。

9. 发明申请

US20070057693A1 Reconfigurable circuit with redundant reconfigurable cluster(S) 有权
标题翻译：具有冗余可重构集群（S）的可重构电路
公开(公告)号：US20070057693A1
公开(公告)日：2007-03-15
申请号：US11225750
申请日：2005-09-13
申请人： Frederic Reblewski
发明人： Frederic Reblewski
IPC分类号： H03K19/177
CPC分类号： H03K19/17764 , G06F11/2236 , H03K19/17736
摘要： A reconfigurable circuit having redundant reconfigurable clusters is described herein.
摘要翻译：本文描述了具有冗余可重构簇的可重构电路。

10. 发明授权

US07130788B2 Emulation components and system including distributed event monitoring, and testing of an IC design under emulation 有权
标题翻译：仿真组件和系统，包括分布式事件监控，以及仿真下的IC设计测试
公开(公告)号：US07130788B2
公开(公告)日：2006-10-31
申请号：US10003184
申请日：2001-10-30
申请人： Frederic Reblewski
发明人： Frederic Reblewski
IPC分类号： G06F9/455
CPC分类号： G06F17/5027
摘要： Data processing resources are distributively provided to an emulation system to locally and correspondingly generate testing stimuli, and applying the generated testing stimuli to partitions of an IC design to be emulated. In one embodiment, the distributed data processing resources further locally and correspondingly retrieve state data of emulation state circuit elements, analyze the retrieved state data for one or more events, and report the one or more events upon their detection. In one embodiment, the distributed data processing resources are disposed on logic boards of an emulation system. In other embodiments, at least some of the distributed data processing resources are disposed on the emulation ICs of the logic boards.
摘要翻译：数据处理资源被分布式地提供给仿真系统以便本地地并且相应地生成测试刺激，并且将生成的测试刺激应用于待仿真的IC设计的分区。在一个实施例中，分布式数据处理资源进一步在本地并相应地检索仿真状态电路元件的状态数据，分析检索到的一个或多个事件的状态数据，并在其检测时报告一个或多个事件。在一个实施例中，分布式数据处理资源被布置在仿真系统的逻辑板上。在其他实施例中，分布式数据处理资源中的至少一些被布置在逻辑板的仿真IC上。

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