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1. 发明授权

US06828646B2 Isolating trench and manufacturing process 有权
标题翻译：隔离沟槽和制造工艺
公开(公告)号：US06828646B2
公开(公告)日：2004-12-07
申请号：US10272444
申请日：2002-10-16
申请人： Michel Marty , Francois Leverd , Philippe Coronel , Joaquin Torres
发明人： Michel Marty , Francois Leverd , Philippe Coronel , Joaquin Torres
IPC分类号： H01L2900
CPC分类号： H01L21/76229 , H01L21/764
摘要： An isolation trench formed in a semiconductor substrate has side walls and a bottom wall. Spacers are on the side walls and face each other for forming a narrow channel therebetween. The bottom wall and the spacers are coated with an electrically insulating material for delimiting a closed empty cavity in the channel. The isolation trench is applicable to the manufacture of integrated circuits.
摘要翻译：在半导体衬底中形成的隔离沟具有侧壁和底壁。隔板在侧壁上并且彼此面对以在它们之间形成狭窄的通道。底壁和间隔物涂覆有用于限定通道中的封闭空腔的电绝缘材料。隔离沟槽适用于集成电路的制造。

2. 发明授权

US06281068B1 Method for buried plate formation in deep trench capacitors 失效
标题翻译：深沟槽电容器掩埋板形成方法
公开(公告)号：US06281068B1
公开(公告)日：2001-08-28
申请号：US09291453
申请日：1999-04-14
申请人： Philippe Coronel , David Cruau , Francois Leverd , Renzo Maccagnan , Eric Mass
发明人： Philippe Coronel , David Cruau , Francois Leverd , Renzo Maccagnan , Eric Mass
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L21/31138
摘要： An improved method of forming the buried plate regions in deep trench capacitors used in DRAM memory semiconductor circuits in which the polymer used in the deep trench is etched down to the desired depth in a reactive ion etch tool using an O2/CF4 chemistry. Since optical/interferometric etch end-point detection system can be used to monitor the etch back step in its totality, the quantity of the polymer remaining in deep trenches can be very accurately controlled, which in turn will produce a well controlled buried plate region during the out-diffusion step of the arsenic dopant contained in the arsenic doped silicon glass layer.
摘要翻译：在DRAM存储器半导体电路中使用的深沟槽电容器中形成掩埋板区域的改进方法，其中使用O 2 / CF 4化学法在深沟槽中使用的聚合物被蚀刻到反应离子蚀刻工具中的所需深度。由于光学/干涉蚀刻终点检测系统可用于监测其整体的回蚀步骤，所以可以非常精确地控制残留在深沟槽中的聚合物的量，这反过来又将产生良好控制的掩埋板区域包含在砷掺杂硅玻璃层中的砷掺杂物的扩散步骤。

3. 发明授权

US08847344B2 Process for fabricating a backside-illuminated imaging device and corresponding device 有权
标题翻译：用于制造背面照明成像装置和相应装置的方法
公开(公告)号：US08847344B2
公开(公告)日：2014-09-30
申请号：US13483274
申请日：2012-05-30
申请人： Francois Roy , Francois Leverd , Jens Prima
发明人： Francois Roy , Francois Leverd , Jens Prima
IPC分类号： H01L31/0232 , H01L27/146
CPC分类号： H01L27/14632 , H01L27/1464 , H01L27/14643 , H01L27/14689
摘要： An integrated imaging device includes a silicon layer provided over a dielectric multilayer. The dielectric multilayer includes a top silicon-dioxide layer, an intermediate silicon-nitride layer and a bottom silicon-dioxide layer. Imaging circuitry is formed at a frontside of the silicon layer. An isolating structure surrounds the imaging circuitry and extends from the frontside through the silicon layer and top silicon-dioxide layer into and terminating within the intermediate silicon-nitride layer. A filter for the imaging circuitry is mounted to a backside of the bottom silicon-dioxide layer. The isolating structure is formed by a trench filled with a dielectric material.
摘要翻译：集成成像装置包括设置在电介质多层上的硅层。电介质层包括顶部二氧化硅层，中间氮化硅层和底部二氧化硅层。成像电路形成在硅层的前侧。隔离结构围绕成像电路并从前侧穿过硅层和顶部二氧化硅层延伸到中间氮化硅层内并终止于中间氮化硅层内。用于成像电路的滤光器安装在底部二氧化硅层的背面。隔离结构由填充有电介质材料的沟槽形成。

4. 发明申请

US20130052829A1 METHOD FOR PRODUCING A DEEP TRENCH IN A MICROELECTRONIC COMPONENT SUBSTRATE 有权
标题翻译：在微电子元件基板中生产深层电感的方法
公开(公告)号：US20130052829A1
公开(公告)日：2013-02-28
申请号：US13599961
申请日：2012-08-30
申请人： Francois Leverd , Laurent Favennec , Arnaud Tournier
发明人： Francois Leverd , Laurent Favennec , Arnaud Tournier
IPC分类号： H01L21/3065
CPC分类号： H01L21/30655 , H01L21/76224
摘要： A method for producing a deep trench in a substrate includes a series of elementary etch cycles each etching a portion of the trench. Each elementary cycle includes deposition of a passivation layer on the sidewalls and the bottom of the trench portion etched during previous cycles; followed by pulsed plasma anisotropic ion etching of the trench portion etched during previous cycles, the etching; being implemented in an atmosphere comprising a passivating species; and including a first etch sequence followed by a second etch sequence of less power than the power of the first etch sequence. The first etch sequence etches the passivation layer deposited in the bottom of the portion so as to access the substrate and etches the free substrate at the bottom of the portion while leaving a passivation layer on sidewalls of the portion.
摘要翻译：用于在衬底中制造深沟槽的方法包括一系列基本蚀刻循环，每个蚀刻循环蚀刻沟槽的一部分。每个基本循环包括在先前循环中蚀刻的沟槽部分的侧壁和底部上沉积钝化层; 随后是在先前循环中蚀刻的沟槽部分的脉冲等离子体各向异性离子蚀刻，蚀刻; 在包括钝化物种的气氛中实施; 并且包括第一蚀刻序列，随后是比第一蚀刻序列的功率小的功率的第二蚀刻序列。第一蚀刻序列蚀刻沉积在该部分的底部中的钝化层，以便访问该衬底并在该部分的底部蚀刻自由衬底，同时在该部分的侧壁上留下钝化层。

5. 发明申请

US20050191818A1 Integrated circuit with a strongly-conductive buried layer 有权
标题翻译：具有强导电性埋层的集成电路
公开(公告)号：US20050191818A1
公开(公告)日：2005-09-01
申请号：US11123318
申请日：2005-05-06
申请人： Michel Marty , Philippe Coronel , Francois Leverd
发明人： Michel Marty , Philippe Coronel , Francois Leverd
IPC分类号： H01L29/73 , H01L21/331 , H01L29/08 , H01L29/417 , H01L29/732
CPC分类号： H01L29/66272 , H01L29/0821 , H01L29/41708
摘要： An integrated circuit including a buried layer of determined conductivity type in a plane substantially parallel to the plane of a main circuit surface, in which the median portion of this buried layer is filled with a metal-type material.
摘要翻译：一种集成电路，其包括在基本上平行于主电路表面的平面的平面中确定的导电类型的掩埋层，其中该掩埋层的中间部分填充有金属型材料。

6. 发明授权

US06689655B2 Method for production process for the local interconnection level using a dielectric conducting pair on pair 有权
标题翻译：使用一对电介质导电对的局部互连电平的制造工艺方法
公开(公告)号：US06689655B2
公开(公告)日：2004-02-10
申请号：US10081296
申请日：2002-02-20
申请人： Philippe Coronel , Francois Leverd , Paul Ferreira
发明人： Philippe Coronel , Francois Leverd , Paul Ferreira
IPC分类号： H01L218234
CPC分类号： H01L21/76897 , H01L21/76831 , H01L21/76841
摘要： The invention relates to a process for protection of the grid of a transistor in an integrated circuit for production of a local interconnection pad straddling over the grid and the silicon substrate on which it is formed. The process consists of applying a double dielectric-conducting layer on the transistor grid into which a polysilicon layer is added in order to use the selectivity principle, which is large considering the etching of polysilicon with respect to the oxide in which the local interconnection pad is formed. Furthermore, with the process according to the invention, a silicidation treatment can be applied beforehand on the active areas of the transistor and the grid.
摘要翻译：本发明涉及一种用于保护集成电路中的晶体管栅格的方法，用于制造跨越栅极的局部互连焊盘和形成在其上的硅衬底。该方法包括在晶体管栅格上施加双电介质传导层，其中添加多晶硅层以便使用选择性原理，考虑到多晶硅相对于本地互连衬垫是形成。此外，根据本发明的方法，可以预先在晶体管和栅极的有源区上施加硅化处理。

7. 发明申请

US20120306035A1 PROCESS FOR FABRICATING A BACKSIDE-ILLUMINATED IMAGING DEVICE AND CORRESPONDING DEVICE 有权
标题翻译：背景照明成像装置和相关装置的制作方法
公开(公告)号：US20120306035A1
公开(公告)日：2012-12-06
申请号：US13483274
申请日：2012-05-30
申请人： Francois Roy , Francois Leverd , Jens Prima
发明人： Francois Roy , Francois Leverd , Jens Prima
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： H01L27/14632 , H01L27/1464 , H01L27/14643 , H01L27/14689
摘要： An integrated imaging device includes a silicon layer provided over a dielectric multilayer. The dielectric multilayer includes a top silicon-dioxide layer, an intermediate silicon-nitride layer and a bottom silicon-dioxide layer. Imaging circuitry is formed at a frontside of the silicon layer. An isolating structure surrounds the imaging circuitry and extends from the frontside through the silicon layer and top silicon-dioxide layer into and terminating within the intermediate silicon-nitride layer. A filter for the imaging circuitry is mounted to a backside of the bottom silicon-dioxide layer. The isolating structure is formed by a trench filled with a dielectric material.
摘要翻译：集成成像装置包括设置在电介质多层上的硅层。电介质层包括顶部二氧化硅层，中间氮化硅层和底部二氧化硅层。成像电路形成在硅层的前侧。隔离结构围绕成像电路并从前侧穿过硅层和顶部二氧化硅层延伸到中间氮化硅层内并终止于中间氮化硅层内。用于成像电路的滤光器安装在底部二氧化硅层的背面。隔离结构由填充有电介质材料的沟槽形成。

8. 发明授权

US07214597B2 Electronic components and method of fabricating the same 有权
标题翻译：电子部件及其制造方法
公开(公告)号：US07214597B2
公开(公告)日：2007-05-08
申请号：US10421368
申请日：2003-04-23
申请人： Philippe Coronel , Francois Leverd , Thomas Skotnicki
发明人： Philippe Coronel , Francois Leverd , Thomas Skotnicki
IPC分类号： H01L21/46 , H01L21/30
CPC分类号： H01L21/6835 , H01L21/32134 , H01L21/76251 , H01L23/544 , H01L27/10852 , H01L27/1087 , H01L27/10873 , H01L27/1203 , H01L28/91 , H01L29/66484 , H01L29/66772 , H01L29/7831 , H01L29/78645 , H01L29/78648 , H01L51/0013 , H01L2221/68363 , H01L2223/54426 , H01L2223/54453 , H01L2224/83894 , H01L2924/01019 , H01L2924/01079 , H01L2924/13091 , H01L2924/19041 , H01L2924/00
摘要： A method is provided for fabricating integrated electronic components. According to the method, an initial structure is produced on the surface of a first substrate. This initial structure incorporates a defined pattern formed from volumes of differentiated materials. At least part of the initial substrate that includes the defined pattern is transferred onto a second substrate, preferably by inverting the first substrate against the second substrate and then removing the first substrate. An additional structure is then produced on the second substrate. This additional structure includes volumes of material placed in correspondence with some of the volumes of differentiated material of the defined pattern. The electronic components thus produced may have a suitable configuration in accordance with technological or geometrical constraints. In a preferred method, a selective treatment is applied to the transferred part of the initial structure, so as to make a distinction between the volumes of differentiated material of the pattern.
摘要翻译：提供了一种用于制造集成电子部件的方法。根据该方法，在第一基板的表面上产生初始结构。该初始结构包含由差异化材料体积形成的限定图案。包括限定图案的初始衬底的至少一部分被转移到第二衬底上，优选地通过使第一衬底相对于第二衬底反转，然后去除第一衬底。然后在第二基板上产生另外的结构。该附加结构包括与限定图案的一些体积不同的材料相对应放置的材料体积。如此制造的电子部件可以根据技术或几何约束具有合适的构造。在优选的方法中，对初始结构的转移部分应用选择性处理，以区分图案的差异材料的体积。

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