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    • 1. 发明授权
    • Method and apparatus for booting a microprocessor system using boot code stored on a serial flash memory array having a random-access interface
    • 使用存储在具有随机存取接口的串行闪存阵列上的引导代码引导微处理器系统的方法和装置
    • US07908466B2
    • 2011-03-15
    • US11554627
    • 2006-10-31
    • Jee-Woong OhEun-Seok ChaeShin-Kyu Park
    • Jee-Woong OhEun-Seok ChaeShin-Kyu Park
    • G06F12/00
    • G06F9/4401G06F8/65
    • A method and apparatus for booting a microprocessor system using a serial (e.g., NAND-type) flash memory array having a random-access (parallel, e.g., NOR-flash type) interface. The method includes loading a boot code loader stored in the serial (e.g., NAND-type) flash memory array into a RAM when power is turned on, according to a routine of a read-only memory (ROM) of the microprocessor; loading boot code stored in the serial flash memory into an internal or external (main) RAM of the microprocessor according to the boot code loader; loading application code stored in the serial flash memory into the main (RAM) memory according to the boot code; and executing the application code. The system may be manufactured at a low cost compared to NOR-Flash based systems, while ensuring flexibility of a microprocessor.
    • 一种使用具有随机存取(并行,例如NOR闪存型)接口的串行(例如NAND型)闪速存储器阵列引导微处理器系统的方法和装置。 该方法包括:根据微处理器的只读存储器(ROM)的例程,将电源接通时将存储在串行(例如,NAND型)闪存阵列中的引导代码加载器加载到RAM中; 根据引导代码加载器将存储在串行闪存中的引导代码加载到微处理器的内部或外部(主)RAM中; 根据引导代码将存储在串行闪存中的应用代码加载到主(RAM)存储器中; 并执行应用程序代码。 与基于NOR-Flash的系统相比,该系统可以以低成本制造,同时确保微处理器的灵活性。
    • 2. 发明授权
    • Semiconductor integrated circuit including circuit for selecting embedded tap cores
    • 包括用于选择嵌入式抽头核心的电路的半导体集成电路
    • US06691289B2
    • 2004-02-10
    • US10086144
    • 2002-02-28
    • Eun-seok ChaeGyoo-chan Sim
    • Eun-seok ChaeGyoo-chan Sim
    • G06F1750
    • G01R31/318563
    • A semiconductor integrated circuit satisfying the IEEE 1149.1 standard and allowing all test access port (TAP) cores embedded in a chip to be tested on a circuit board as well as on a chip is provided. The semiconductor integrated circuit includes a plurality of TAP cores sharing a test data input pin, a test mode selection signal input pin, a test reset signal input pin, and a test clock signal input pin. An input port of a boundary scan register circuit is connected to the test data input pin. Input ports of a selection signal generating circuit are connected to the test data input pin, the test reset signal input pin, and the test clock signal input pin. The selection signal generating circuit generates selection signals for selecting one of the plurality of TAP cores and the boundary scan register circuit in response to signals input through these input pins. A selector selects one of the outputs of the plurality of TAP cores and the boundary scan register circuit in response to the selection signals and outputs the selection to an output pin.
    • 提供满足IEEE 1149.1标准并允许嵌入在芯片中的所有测试访问端口(TAP)内核在电路板以及芯片上进行测试的半导体集成电路。 半导体集成电路包括共享测试数据输入引脚的多个TAP核,测试模式选择信号输入引脚,测试复位信号输入引脚和测试时钟信号输入引脚。 边界扫描寄存器电路的输入端口连接到测试数据输入引脚。 选择信号发生电路的输入端口连接到测试数据输入引脚,测试复位信号输入引脚和测试时钟信号输入引脚。 选择信号发生电路响应于通过这些输入引脚输入的信号,产生用于选择多个TAP核和边界扫描寄存器电路中的一个的选择信号。 选择器响应于选择信号选择多个TAP核和边界扫描寄存器电路中的一个输出,并将选择输出到输出引脚。
    • 3. 发明授权
    • Apparatus and method for parallel testing of multiple functional blocks of an integrated circuit
    • 用于并行测试集成电路的多个功能块的装置和方法
    • US06546511B1
    • 2003-04-08
    • US09478162
    • 2000-01-05
    • Gyoo-chan SimEun-seok Chae
    • Gyoo-chan SimEun-seok Chae
    • G01R3128
    • G11C29/26G01R31/3187G11C2029/2602
    • Functional blocks of an integrated circuit are tested in real time using a restricted number of output pins. The apparatus of the invention comprises an integrated circuit including a plurality of functional blocks, each of which, in response to a given stimulus, generates a similar output. The apparatus includes: a comparator for comparing the levels of like output signals from each of the functional blocks and for outputting the comparison result; a transmitter for external transmission of one of the output signals in response to the comparison result; and a failure discriminator for comparing the transmitted output signal level to a predetermined target output signal level, and if similar, transmitting a positive test result signal.
    • 使用有限数量的输出引脚实时测试集成电路的功能块。 本发明的装置包括集成电路,其包括多个功能块,每个功能块响应于给定的刺激而产生类似的输出。 该装置包括:比较器,用于比较来自每个功能块的类似输出信号的电平,并输出比较结果; 用于响应比较结果外部传输一个输出信号的发射机; 以及用于将发送的输出信号电平与预定的目标输出信号电平进行比较的故障鉴别器,如果相似,则发送正的测试结果信号。
    • 4. 发明申请
    • METHOD AND APPARATUS FOR BOOTING A MICROPROCESSOR SYSTEM USING BOOT CODE STORED ON A SERIAL FLASH MEMORY ARRAY HAVING A RANDOM-ACCESS INTERFACE
    • 使用存储在具有随机访问接口的串行闪速存储器阵列上的引导代码来对微处理器系统进行操作的方法和装置
    • US20070113067A1
    • 2007-05-17
    • US11554627
    • 2006-10-31
    • Jee-Woong OhEun-Seok ChaeShin-Kyu Park
    • Jee-Woong OhEun-Seok ChaeShin-Kyu Park
    • G06F15/177
    • G06F9/4401G06F8/65
    • A method and apparatus for booting a microprocessor system using a serial (e.g., NAND-type) flash memory array having a random-access (parallel, e.g., NOR-flash type) interface. The method includes loading a boot code loader stored in the serial (e.g., NAND-type) flash memory array into a RAM when power is turned on, according to a routine of a read-only memory (ROM) of the microprocessor; loading boot code stored in the serial flash memory into an internal or external (main) RAM of the microprocessor according to the boot code loader; loading application code stored in the serial flash memory into the main (RAM) memory according to the boot is code; and executing the application code. The system may be manufactured at a low cost compared to NOR-Flash based systems, while ensuring flexibility of a microprocessor.
    • 一种使用具有随机存取(并行,例如NOR闪存型)接口的串行(例如NAND型)闪速存储器阵列引导微处理器系统的方法和装置。 该方法包括:根据微处理器的只读存储器(ROM)的例程,将电源接通时将存储在串行(例如,NAND型)闪存阵列中的引导代码加载器加载到RAM中; 根据引导代码加载器将存储在串行闪存中的引导代码加载到微处理器的内部或外部(主)RAM中; 根据引导将存储在串行闪存中的应用代码加载到主(RAM)存储器中是代码; 并执行应用程序代码。 与基于NOR-Flash的系统相比,该系统可以以低成本制造,同时确保微处理器的灵活性。