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1. 发明授权

US06573742B2 Semiconductor integrated circuit with test points inserted thereinto 有权
公开(公告)号：US06573742B2
公开(公告)日：2003-06-03
申请号：US09828879
申请日：2001-04-10
申请人： Gyoo-Chan Sim
发明人： Gyoo-Chan Sim
IPC分类号： G01R3128
CPC分类号： G01R31/318572
摘要： A semiconductor integrated circuit device includes a logic circuit having a plurality of observation points and a control point, a plurality of scan cells, a first multiplexer for selecting one of normal data supplied from the logic circuit or one of data supplied from the one or more observation points and outputting the selected data, and a second multiplexer for outputting one of the normal data and scan data supplied from the scan cells to the control point. A select signal for selecting outputs of the first and second multiplexers may be an output of a scan cell of the device. When test points are inserted into a scan-designed circuit, the device may use existing cells constructed therein to minimize the number of added pins. Thus, it is possible to maximally enhance testability with minimal overhead.

2. 发明授权

US06199184B1 Parallel signature compression circuit and method for designing the same 有权
标题翻译：并行签名压缩电路及其设计方法
公开(公告)号：US06199184B1
公开(公告)日：2001-03-06
申请号：US09149380
申请日：1998-09-08
申请人： Gyoo-Chan Sim
发明人： Gyoo-Chan Sim
IPC分类号： G01R3128
CPC分类号： G01R31/318547
摘要： A parallel signature compression circuit includes two or more MISRs (multiple input signature registers) coupled in series. The signature compression circuit allows the error effect of at least one of two repetitive error patterns to be transferred to a cell other than the cell where the error effect is counterbalanced. In an embodiment, a signature compression circuit has two MISRs and prevents the error masking due to the repetitive error patterns of the odd-numbered distances. In another embodiment, in order to reduce the error masking by the repetitive error patterns with even-numbered distances, the repetitive error patterns are compressed as many times as possible within the range of design rule.
摘要翻译：并行签名压缩电路包括串联耦合的两个或多个MISR（多个输入签名寄存器）。签名压缩电路允许将两个重复错误模式中的至少一个的误差效应传送到除了误差效应被平衡的单元之外的单元。在一个实施例中，签名压缩电路具有两个MISR，并且防止由于奇数距离的重复错误模式引起的错误掩蔽。在另一个实施例中，为了通过具有偶数距离的重复误差模式来减少误差掩蔽，重复误差模式在设计规则的范围内被压缩多次。

3. 发明授权

US6125460A Method for testing semiconductor device having embedded nonvolatile memory 有权
标题翻译：具有嵌入式非易失性存储器的半导体器件测试方
公开(公告)号：US6125460A
公开(公告)日：2000-09-26
申请号：US168633
申请日：1998-10-08
申请人： Gyoo-chan Sim
发明人： Gyoo-chan Sim
IPC分类号： G01R31/28 , G01R31/3183 , G11C29/00 , G11C29/56
CPC分类号： G01R31/318371
摘要： A method for testing a semiconductor device having a logic, a nonvolatile memory and a code generator for generating a code in response to the output of the nonvolatile memory is provided. The method includes the steps of loading a program, generating a code, inputting the code, testing the nonvolatile memory, comparing, checking the test response, revising the test program, and testing the semiconductor device. Specifically, the test program is loaded on the tester. Then a code is generated from memory data stored in the nonvolatile memory, and the code is input into the tester. The nonvolatile memory of the semiconductor device is tested, and the test response output from the code generator is stored in a predetermined memory of the tester. The test response is compared with the code, and the code is replaced by the test response if the test response and the code are the same with each other. Then, the test responses for obtaining the test response having a high level of precision is checked by comparing the test response with each other several times. The test program is revised by incorporating the test response into the test program. The semiconductor device is tested using the revised test program.
摘要翻译：提供一种用于测试具有逻辑的半导体器件的方法，非易失性存储器和用于响应于非易失性存储器的输出而产生代码的代码发生器。该方法包括加载程序，生成代码，输入代码，测试非易失性存储器，比较，检查测试响应，修改测试程序以及测试半导体器件的步骤。具体来说，测试程序被加载到测试仪上。然后，从存储在非易失性存储器中的存储器数据生成代码，并将代码输入到测试器中。测试半导体器件的非易失性存储器，并且将来自代码发生器的测试响应输出存储在测试器的预定存储器中。将测试响应与代码进行比较，如果测试响应和代码彼此相同，则代码将被测试响应替换。然后，通过将测试响应彼此进行几次比较来检查用于获得具有高精度的测试响应的测试响应。通过将测试响应并入测试程序来修改测试程序。使用修订的测试程序测试半导体器件。

4. 发明授权

US06691289B2 Semiconductor integrated circuit including circuit for selecting embedded tap cores 有权
标题翻译：包括用于选择嵌入式抽头核心的电路的半导体集成电路
公开(公告)号：US06691289B2
公开(公告)日：2004-02-10
申请号：US10086144
申请日：2002-02-28
申请人： Eun-seok Chae , Gyoo-chan Sim
发明人： Eun-seok Chae , Gyoo-chan Sim
IPC分类号： G06F1750
CPC分类号： G01R31/318563
摘要： A semiconductor integrated circuit satisfying the IEEE 1149.1 standard and allowing all test access port (TAP) cores embedded in a chip to be tested on a circuit board as well as on a chip is provided. The semiconductor integrated circuit includes a plurality of TAP cores sharing a test data input pin, a test mode selection signal input pin, a test reset signal input pin, and a test clock signal input pin. An input port of a boundary scan register circuit is connected to the test data input pin. Input ports of a selection signal generating circuit are connected to the test data input pin, the test reset signal input pin, and the test clock signal input pin. The selection signal generating circuit generates selection signals for selecting one of the plurality of TAP cores and the boundary scan register circuit in response to signals input through these input pins. A selector selects one of the outputs of the plurality of TAP cores and the boundary scan register circuit in response to the selection signals and outputs the selection to an output pin.
摘要翻译：提供满足IEEE 1149.1标准并允许嵌入在芯片中的所有测试访问端口（TAP）内核在电路板以及芯片上进行测试的半导体集成电路。半导体集成电路包括共享测试数据输入引脚的多个TAP核，测试模式选择信号输入引脚，测试复位信号输入引脚和测试时钟信号输入引脚。边界扫描寄存器电路的输入端口连接到测试数据输入引脚。选择信号发生电路的输入端口连接到测试数据输入引脚，测试复位信号输入引脚和测试时钟信号输入引脚。选择信号发生电路响应于通过这些输入引脚输入的信号，产生用于选择多个TAP核和边界扫描寄存器电路中的一个的选择信号。选择器响应于选择信号选择多个TAP核和边界扫描寄存器电路中的一个输出，并将选择输出到输出引脚。

5. 发明授权

US06546511B1 Apparatus and method for parallel testing of multiple functional blocks of an integrated circuit 有权
标题翻译：用于并行测试集成电路的多个功能块的装置和方法
公开(公告)号：US06546511B1
公开(公告)日：2003-04-08
申请号：US09478162
申请日：2000-01-05
申请人： Gyoo-chan Sim , Eun-seok Chae
发明人： Gyoo-chan Sim , Eun-seok Chae
IPC分类号： G01R3128
CPC分类号： G11C29/26 , G01R31/3187 , G11C2029/2602
摘要： Functional blocks of an integrated circuit are tested in real time using a restricted number of output pins. The apparatus of the invention comprises an integrated circuit including a plurality of functional blocks, each of which, in response to a given stimulus, generates a similar output. The apparatus includes: a comparator for comparing the levels of like output signals from each of the functional blocks and for outputting the comparison result; a transmitter for external transmission of one of the output signals in response to the comparison result; and a failure discriminator for comparing the transmitted output signal level to a predetermined target output signal level, and if similar, transmitting a positive test result signal.
摘要翻译：使用有限数量的输出引脚实时测试集成电路的功能块。本发明的装置包括集成电路，其包括多个功能块，每个功能块响应于给定的刺激而产生类似的输出。该装置包括：比较器，用于比较来自每个功能块的类似输出信号的电平，并输出比较结果; 用于响应比较结果外部传输一个输出信号的发射机; 以及用于将发送的输出信号电平与预定的目标输出信号电平进行比较的故障鉴别器，如果相似，则发送正的测试结果信号。

6. 发明授权

US06374380B1 Boundary scan cells to improve testability of core-embedded circuits 失效
标题翻译：边界扫描单元，以提高核心嵌入式电路的可测试性
公开(公告)号：US06374380B1
公开(公告)日：2002-04-16
申请号：US09393001
申请日：1999-09-09
申请人： Gyoo-Chan Sim
发明人： Gyoo-Chan Sim
IPC分类号： G01R3128
CPC分类号： G01R31/318536
摘要： As system-on-a-chip (SOC) designs become popular these days, the number of embedded cores in a chip gets larger, raising test issues of glue logic test as well as embedded core test. A core-embedded integrated circuit comprising a first logic block, a second logic block, a signal line coupled between the first logic block and the second logic block for inputting/outputting an input/output signal of the logic blocks, and a boundary scan cell coupled to the signal line for loading /capturing the input/output signal for testing one or both of the first logic block and the second logic block (individually or together), with minimum overhead. Each boundary scan cell includes a data holding capability for data loading from the first and/or second logic block, wherein each boundary scan cell is adapted for serial connection with another of a plurality of like boundary scan cells (boundary scan cell chaining). The boundary scan cells according to the present invention increase testability of the glue logic and the cores with minimal overhead and simple test control, in contrast with a prior art Joint Test Action Group (JTAG) boundary scan design method.
摘要翻译：随着系统级芯片（SOC）的设计越来越受欢迎，芯片内嵌的内核数量变得越来越大，提高了胶合逻辑测试以及嵌入式核心测试的测试问题。核心嵌入式集成电路，包括第一逻辑块，第二逻辑块，耦合在第一逻辑块和第二逻辑块之间的信号线，用于输入/输出逻辑块的输入/输出信号;以及边界扫描单元耦合到用于加载/捕获用于以最小开销测试第一逻辑块和第二逻辑块（单独地或一起）中的一个或两个的输入/输出信号的信号线。每个边界扫描单元包括用于从第一和/或第二逻辑块进行数据加载的数据保持能力，其中每个边界扫描单元适于与多个相似的边界扫描单元（边界扫描单元链接）中的另一个进行串行连接。与现有技术的联合测试动作组（JTAG）边界扫描设计方法相比，根据本发明的边界扫描单元以最小的开销和简单的测试控制提高了胶合逻辑和核心的可测试性。

7. 发明授权

US06240537B1 Signature compression circuit and method 有权
标题翻译：签名压缩电路及方法
公开(公告)号：US06240537B1
公开(公告)日：2001-05-29
申请号：US09148963
申请日：1998-09-08
申请人： Gyoo-Chan Sim
发明人： Gyoo-Chan Sim
IPC分类号： G01R3128
CPC分类号： G01R31/318547
摘要： A parallel signature compression circuit allows the error effect of at least one of two repetitive error patterns to be transferred to a cell other than the cell where the error effect is counterbalanced. In an embodiment, a signature pattern from a circuit to be tested is latched, and then the latched pattern is compressed two or more times until a next signature pattern is outputted from the circuit to be test. The compression is performed by shifting the latched pattern serially by use of a multiple input signature register.
摘要翻译：并行签名压缩电路允许两个重复错误模式中的至少一个的误差效应被传送到除了误差效应被平衡的单元之外的单元。在一个实施例中，锁存来自被测试电路的签名模式，然后将锁存模式压缩两次或更多次，直到从要测试的电路输出下一个签名模式。通过使用多输入签名寄存器来串行移位锁存模式来执行压缩。

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