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    • 7. 发明授权
    • Address/control signal input circuit for a cache controller which clamps
the address/control signals to predetermined logic level clamp signal
is received
    • 接收用于将地址/控制信号钳位到预定逻辑电平钳位信号的高速缓存控制器的地址/控制信号输入电路
    • US5179678A
    • 1993-01-12
    • US637962
    • 1991-01-09
    • Eiji Kawamura
    • Eiji Kawamura
    • G06F12/08
    • G06F12/0802
    • A cache controller is coupled to a cache memory coupled through a bus to a microprocessor, for controlling the cache memory in response to a signal from the microprocessor. The cache controller comprises an address signal terminal and a control signal terminal for receiving an address signal and a control signal from the microprocessor, and a clamp signal terminal for receiving a clamp signal from the microprocessor. The cache controller also includes an input circuit coupled to the address signal terminal, the control signal terminal and the clamp signal terminal for outputting the address signal and the control signal as they are when the clamp signal is inactive and for generating an output address signal and an ouput control signal having a predetermined logic level when the clamp signal is active.
    • 高速缓存控制器耦合到通过总线耦合到微处理器的高速缓冲存储器,用于响应于来自微处理器的信号来控制高速缓冲存储器。 高速缓存控制器包括地址信号端子和用于从微处理器接收地址信号和控制信号的控制信号端子,以及用于从微处理器接收钳位信号的钳位信号端子。 高速缓存控制器还包括耦合到地址信号端子,控制信号端子和钳位信号端子的输入电路,用于当钳位信号无效时输出地址信号和控制信号,并产生输出地址信号, 当钳位信号有效时具有预定逻辑电平的输出控制信号。