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1. 发明申请

US20130321205A1 Method And Apparatus For Analyzing A System Design Having A Phased Array Antenna 审中-公开
标题翻译：用于分析具有相控阵天线的系统设计的方法和装置
公开(公告)号：US20130321205A1
公开(公告)日：2013-12-05
申请号：US13486340
申请日：2012-06-01
申请人： Mark J. Beals , Edgar J. Martinez , Jacob Kim , Ajay Subramanian , William F. Skalenda , Robert W. Alm , Lee A. McMillan
发明人： Mark J. Beals , Edgar J. Martinez , Jacob Kim , Ajay Subramanian , William F. Skalenda , Robert W. Alm , Lee A. McMillan
IPC分类号： H01Q3/00
CPC分类号： H01Q3/267 , G06F17/5009 , H04B7/0617
摘要： Disclosed subject matter is directed to techniques and systems for analyzing a system design having a phase array antenna. In at least one implementation, component models of individual components of the phased array antenna may be provided. The component models may be arranged as a multi-dimensional lookup table (LUT) in some embodiments. A single-channel model of antenna performance may be synthesized for the system design based on the component models. An analysis of the performance of the system design may then be performed using the single-channel model of antenna performance.
摘要翻译：公开的主题涉及用于分析具有相位阵列天线的系统设计的技术和系统。在至少一个实现中，可以提供相控阵天线的各个部件的组件模型。在一些实施例中，组件模型可以被布置为多维查找表（LUT）。可以基于组件模型为系统设计合成单通道天线性能模型。然后可以使用单通道天线性能模型来执行系统设计的性能分析。

2. 发明授权

US5192698A Making staggered complementary heterostructure FET 失效
标题翻译：交错互补异质结FET
公开(公告)号：US5192698A
公开(公告)日：1993-03-09
申请号：US853150
申请日：1992-03-17
申请人： Fritz L. Schuermeyer , Paul E. Cook , Edgar J. Martinez , Marino J. Martinez
发明人： Fritz L. Schuermeyer , Paul E. Cook , Edgar J. Martinez , Marino J. Martinez
IPC分类号： H01L21/8252
CPC分类号： H01L21/8252 , Y10S148/065 , Y10S148/072
摘要： It is desirable to implement complementary field effect transistors in group III/group V compound semiconductors, especially on InP substrates. Outstanding n-channel performance has been demonstrated in InGaAs channel devices on InP substrates. Preliminary experiments indicate that GaAsSb channel devices will result in optimal p-heterostructure FETs (HFETs). This disclosure teaches a technique to fabricate both n- and p-channel devices on the same substrate, allowing the demonstration of (C-HFET) technology. The HFET structure contains a channel region and the barrier region. The channel region consists of two distinctive parts: the p-channel and the n-channel areas. The p-channel area consists of GaAsSb, lattice matched to the InP substrate. In n-channel FETs, and ohmic contacts are formed by first doping the contact areas with Si by ion implantation, annealing the structure and then depositing and annealing the ohmic metal. In the complementary FET p-channel FETs, BE ion implementation is used for formation of ohmic contacts.
摘要翻译：期望在III / V族化合物半导体中实现互补的场效应晶体管，特别是在InP衬底上。 InPAs沟道器件在InP衬底上已经证明了出色的n沟道性能。初步实验表明，GaAsSb通道器件将产生最佳的p-异质结构FET（HFET）。该公开内容教导了在同一衬底上制造n沟道器件和p沟道器件的技术，允许演示（C-HFET）技术。 HFET结构包含沟道区和屏障区。通道区域由两个不同的部分组成：p沟道和n沟道区域。 p沟道区域由GaAsSb组成，与InP衬底晶格匹配。在n沟道FET中，通过用Si离子注入首先掺杂接触区域来形成欧姆接触，退火结构，然后沉积和退火欧姆金属。在互补FET p沟道FET中，BE离子实现用于形成欧姆接触。

3. 发明授权

US5429963A Twin-tub complementary heterostructure field effect transistor fab process 失效
标题翻译：双槽互补异质结构场效应晶体管工艺
公开(公告)号：US5429963A
公开(公告)日：1995-07-04
申请号：US232978
申请日：1994-04-25
申请人： Edgar J. Martinez , Michael Shur , Fritz Schuermeyer , Charles Cerny
发明人： Edgar J. Martinez , Michael Shur , Fritz Schuermeyer , Charles Cerny
IPC分类号： H01L21/8252 , H01L27/06 , H01L27/092 , H01L21/331
CPC分类号： H01L21/8252 , H01L27/0605 , H01L27/0922
摘要： This is a fabrication process for complementary III-V HFETs in which devices are built side-by-side in doped-areas, known as "tubs", grown by molecular beam epitaxy on indium phosphide (InP) substrates, or other material systems such as materials grown on GaAs substrates. The layers grown are a semi-insulating buffer layer of InAlAs, a InGaAs channel, an InAlAs barrier layer and finally an InGaAs cap layer. All layers are lattice matched or pseudomorphic to the InP substrate. After mesa etching of areas around the transistor, a high temperature silicon nitride (Si.sub.3 N.sub.4) layer is deposited using chemical vapor deposition, and photoresist is deposited. Then n-well and p-well areas are formed in turn, with appropriate ion-implantation, stripping of the photoresist, and annealing to activate the dopants. Then the Si.sub.3 N.sub.4 is stripped and the samples thoroughly cleaned. Then, the refractory gate metal is sputtered, delineated with photoresist and reactive ion etch procedures. Areas for n-ohmic and p-ohmic contacts are formed, using with Si.sub.3 N.sub.4 and photoresist covering, ion implanting, and annealing. Finally the p- and n-ohmic contact metals are evaporated and alloyed. The typical n-ohmic metal system is Au/Ge/Ni while Au/Zn is used for the formation of the p-ohmic contacts. The integrated circuit is completed by depositing and patterning the interconnect metal.
摘要翻译：这是互补III-V HFET的制造工艺，其中器件在掺杂区域（称为“桶”）中并排构建，通过磷化铟（InP）衬底上的分子束外延生长，或其他材料系统作为在GaAs衬底上生长的材料。所生长的层是InAlAs，InGaAs沟道，InAlAs阻挡层和最终为InGaAs覆盖层的半绝缘缓冲层。所有层与InP衬底晶格匹配或伪构。在晶体管周围区域的台面蚀刻之后，使用化学气相沉积沉积高温氮化硅（Si 3 N 4）层，并沉积光致抗蚀剂。然后依次形成n阱和p阱区，通过适当的离子注入，剥离光致抗蚀剂，并退火以激活掺杂剂。然后将Si3N4剥离，样品彻底清洗。然后，溅射耐火栅极金属，用光致抗蚀剂和反应离子蚀刻程序描绘。使用Si3N4和光致抗蚀剂覆盖，离子注入和退火，形成用于n-欧姆和p-欧姆接触的区域。最后，p型和n型欧姆接触金属被蒸发并合金化。典型的n欧姆金属系统是Au / Ge / Ni，而Au / Zn用于形成p欧姆接触。集成电路通过沉积和图案化互连金属而完成。

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