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1. 发明授权

US07851881B1 Schottky barrier diode (SBD) and its off-shoot merged PN/Schottky diode or junction barrier Schottky (JBS) diode 有权
标题翻译：肖特基势垒二极管（SBD）及其截止合并的PN /肖特基二极管或结屏势肖特基（JBS）二极管
公开(公告)号：US07851881B1
公开(公告)日：2010-12-14
申请号：US12365083
申请日：2009-02-03
申请人： Feng Zhao , Bruce Odekirk , Dumitru Sdrulla
发明人： Feng Zhao , Bruce Odekirk , Dumitru Sdrulla
IPC分类号： H01L29/47
CPC分类号： H01L21/0495 , H01L21/046 , H01L24/05 , H01L29/0619 , H01L29/1608 , H01L29/6606 , H01L29/872 , H01L2924/12032 , H01L2924/00
摘要： A merged PN/Schottky diode is provided having a substrate of a first conductivity type and a grid of doped wells of the second conductivity type embedded in the substrate. A Schottky barrier metal layer makes a Schottky barrier contact with the surface of the substrate above the grid. Selected embedded wells in the grid make a Schottky barrier contact to the Schottky barrier metal layer, while most embedded wells do not. The diode forward voltage drop is reduced for the same diode area with reverse blocking benefits similar to a conventional JBS structure.
摘要翻译：提供合并的PN /肖特基二极管，其具有嵌入在衬底中的具有第一导电类型的衬底和第二导电类型的掺杂阱的栅格。肖特基势垒金属层使得肖特基势垒与网格上方的衬底表面接触。栅极中选择的嵌入式阱使肖特基势垒接触肖特基势垒金属层，而大多数嵌入式阱不具有。对于相同的二极管区域，二极管正向压降降低，具有类似于常规JBS结构的反向阻塞效应。

2. 发明申请

US20130256698A1 LOW LOSS SIC MOSFET 有权
标题翻译：低损耗SIC MOSFET
公开(公告)号：US20130256698A1
公开(公告)日：2013-10-03
申请号：US13195632
申请日：2011-08-01
申请人： Dumitru Sdrulla , Bruce Odekirk , Marc Vandenberg
发明人： Dumitru Sdrulla , Bruce Odekirk , Marc Vandenberg
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66666 , H01L21/049 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/42368 , H01L29/66068 , H01L29/7395 , H01L29/7802
摘要： A Vertical Multiple Implanted Silicon Carbide Power MOSFET (VMIMOSFET) includes a first conductivity semiconductor substrate, a first conductivity semiconductor drift layer on the top of the substrate, a multitude of second conductivity layers implanted in the drift layer. The body layer is where the channel is formed. A first conductivity source layer is interspaced appropriately inside of the second conductivity layers. A gate oxide of a certain thickness and another oxide of a different thickness, a greater thickness than the gate oxide, placed in between the body layers but in such way that its shape does not distort the gate oxide in the channel. A charge compensated body layer of the second conductivity formed outside of the channel region and only at specific high electric field locations in the structure. The device and the manufacturing method deliver a power SiC MOSFET with increased frequency of operation and reduced switching losses.
摘要翻译：垂直多重注入碳化硅功率MOSFET（VMIMOSFET）包括第一导电半导体衬底，衬底顶部上的第一导电半导体漂移层，注入漂移层中的多个第二导电层。身体层是形成通道的地方。第一导电源层在第二导电层内适当地间隔开。具有一定厚度的栅极氧化物和不同厚度的另一种氧化物，比栅极氧化物更大的厚度，放置在主体层之间，但是使得其形状不使通道中的栅极氧化物变形。第二导电体的电荷补偿体层形成在沟道区域外部，并且仅在该结构中的特定高电场位置。该器件和制造方法提供功率SiC MOSFET，具有更高的工作频率和更低的开关损耗。

3. 发明授权

US08476691B1 High reliability-high voltage junction termination with charge dissipation layer 有权
标题翻译：具有电荷耗散层的高可靠性 - 高压结端接
公开(公告)号：US08476691B1
公开(公告)日：2013-07-02
申请号：US13030907
申请日：2011-02-18
申请人： Dumitru Sdrulla , Duane Edward Levine , James M. Katana , Martin David Birch
发明人： Dumitru Sdrulla , Duane Edward Levine , James M. Katana , Martin David Birch
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66712 , H01L29/0615 , H01L29/0619 , H01L29/402 , H01L29/404 , H01L29/405 , H01L29/408 , H01L29/66128 , H01L29/66136 , H01L29/66333 , H01L29/7395 , H01L29/7811 , H01L29/8611
摘要： A high voltage power semiconductor device includes high reliability-high voltage junction termination with a charge dissipation layer. An active device area is surrounded by a junction termination structure including one or more regions of a polarity opposite the substrate polarity. A tunneling oxide layer overlays the junction termination area surrounding the active device area in contact with the silicon substrate upper surface. A layer of undoped polysilicon overlays the tunneling oxide layer and spans the junction termination area, with connections to an outer edge of the junction termination structure and to a grounded electrode inside of the active area. The tunneling oxide layer has a thickness that permits hot carriers formed at substrate upper surface to pass through the tunneling oxide layer into the undoped polysilicon layer to be dissipated but sufficient to mitigate stacking faults at the silicon surface.
摘要翻译：高电压功率半导体器件包括具有电荷耗散层的高可靠性 - 高电压结端接。有源器件区域由包括一个或多个与衬底极性相反的极性的区域的接合端接结构包围。隧道氧化物层覆盖与硅衬底上表面接触的有源器件区域周围的接合端接区域。未掺杂的多晶硅层覆盖隧道氧化物层并且跨越接合端接区域，连接到接合端接结构的外边缘和有源区域内的接地电极。隧穿氧化物层的厚度允许在衬底上表面形成的热载流子穿过隧穿氧化物层进入未掺杂的多晶硅层以消散，但足以减轻硅表面的堆垛层错。

4. 发明申请

US20110037139A1 SCHOTTKY BARRIER DIODE (SBD) AND ITS OFF-SHOOT MERGED PN/SCHOTTKY DIODE OR JUNCTION BARRIER SCHOTTKY (JBS) DIODE 审中-公开
标题翻译：肖特基二极管（SBD）及其短路合并PN /肖特基二极管或接线棒肖特基（JBS）二极管
公开(公告)号：US20110037139A1
公开(公告)日：2011-02-17
申请号：US12912539
申请日：2010-10-26
申请人： Feng Zhao , Bruce Odekirk , Dumitru Sdrulla
发明人： Feng Zhao , Bruce Odekirk , Dumitru Sdrulla
IPC分类号： H01L29/872
CPC分类号： H01L21/0495 , H01L21/046 , H01L24/05 , H01L29/0619 , H01L29/1608 , H01L29/6606 , H01L29/872 , H01L2924/12032 , H01L2924/00
摘要： A merged PN/Schottky diode is provided having a substrate of a first conductivity type and a grid of doped wells of the second conductivity type embedded in the substrate. A Schottky barrier metal layer makes a Schottky barrier contact with the surface of the substrate above the grid. Selected embedded wells in the grid may make electrical contact to the Schottky bather metal layer, while most embedded wells do not. The diode forward voltage drop is reduced for the same diode area with reverse blocking benefits similar to a conventional JBS structure.
摘要翻译：提供合并的PN /肖特基二极管，其具有嵌入在衬底中的具有第一导电类型的衬底和第二导电类型的掺杂阱的栅格。肖特基势垒金属层使得肖特基势垒与网格上方的衬底表面接触。网格中选定的嵌入式井可能会与肖特基泳池金属层进行电接触，而大多数嵌入式井不能。对于相同的二极管区域，二极管正向压降降低，具有类似于常规JBS结构的反向阻塞效应。

5. 发明申请

US20070096237A1 DESIGN AND FABRICATION OF RUGGED FRED, POWER MOSFET OR IGBT 有权
标题翻译：铷格栅，功率MOSFET或IGBT的设计和制造
公开(公告)号：US20070096237A1
公开(公告)日：2007-05-03
申请号：US11614897
申请日：2006-12-21
申请人： Shanqi Zhao , Dumitru Sdrulla
发明人： Shanqi Zhao , Dumitru Sdrulla
IPC分类号： H01L31/107
CPC分类号： H01L29/66136 , H01L29/0615 , H01L29/0619 , H01L29/0661 , H01L29/417 , H01L29/861 , H01L29/8611 , Y10S257/927
摘要： An improved Fast Recovery Diode comprises a main PN junction defining a central conduction region for conducting high current in a forward direction and a peripheral field spreading region surrounding the central conduction region for blocking high voltage in the reverse direction. The main PN junction has an avalanche voltage equal to or lower than an avalanche voltage of the peripheral field spreading region so substantially the entire said main PN junction participates in avalanche conduction. This rugged FRED structure can also be formed in MOSFETS, IGBTS and the like.
摘要翻译：改进的快速恢复二极管包括主PN结，其限定用于在正向方向传导高电流的中心导电区域和围绕中心导电区域的外围场扩散区域，用于阻止相反方向的高电压。主PN结的雪崩电压等于或低于外围场扩散区域的雪崩电压，因此基本上整个所述主PN结参与雪崩传导。这种坚固的FRED结构也可以形成在MOSFET，IGBTS等中。

6. 发明授权

US08436367B1 SiC power vertical DMOS with increased safe operating area 有权
标题翻译： SiC功率垂直DMOS，安全操作区域增加
公开(公告)号：US08436367B1
公开(公告)日：2013-05-07
申请号：US13231877
申请日：2011-09-13
申请人： Dumitru Sdrulla , Bruce Odekirk , Marc Vandenberg
发明人： Dumitru Sdrulla , Bruce Odekirk , Marc Vandenberg
IPC分类号： H01L31/0312
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/086 , H01L29/0865 , H01L29/0878 , H01L29/1033 , H01L29/105 , H01L29/1095 , H01L29/1608 , H01L29/42368 , H01L29/4238 , H01L29/456 , H01L29/66068
摘要： A SiC Power Semiconductor device of the Field Effect Type (MOSFET, IGBT or the like) with “muted” channel conduction, negative temperature coefficient of channel mobility, in situ “ballasted” source resistors and optimized thermal management of the cells for increased Safe Operating Area is described. Controlling the location of the Zero Temperature Crossover Point (ZTCP) in relationship to the drain current is achieved by the partition between the “active” and “inactive” channels and by adjusting the mobility of the carriers in the channel for the temperature range of interest. The “Thermal management” is realized by surrounding the “active” cells/fingers with “inactive” ones and the “negative” feedback of the drain/collector current due to local increase of the gate bias is achieved by implementing in-situ “ballast” resistors inside of each source contact.
摘要翻译：具有“静音”通道导通，沟道迁移的负温度系数，原位“镇流”源电阻的场效应型（MOSFET，IGBT等）的SiC功率半导体器件，并优化了电池的热管理，从而提高了安全运行描述区域。通过“有源”和“非活动”通道之间的分配，并通过调整感兴趣的温度范围的通道中的载流子的迁移率来实现与漏极电流相关的零温度交叉点（ZTCP）的位置控制。 “热管理”是通过围绕“活动”电池/手指“无效”来实现的，并且由于栅极偏置的局部增加引起的漏极/集电极电流的“负”反馈通过实现原位“镇流器 “每个源触点内部的电阻。

7. 发明申请

US20090072340A1 EDGE TERMINATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICE 有权
标题翻译：高压半导体器件的边沿端接
公开(公告)号：US20090072340A1
公开(公告)日：2009-03-19
申请号：US12206954
申请日：2008-09-09
申请人： Jinshu Zhang , Dumitru Sdrulla , Dah Wen Tsang
发明人： Jinshu Zhang , Dumitru Sdrulla , Dah Wen Tsang
IPC分类号： H01L29/06 , H01L21/76
CPC分类号： H01L29/66712 , H01L21/761 , H01L29/0619 , H01L29/0638 , H01L29/0878 , H01L29/404 , H01L29/7811
摘要： High voltage semiconductor devices with high-voltage termination structures are constructed on lightly doped substrates. Lightly doped p-type substrates are particularly prone to depletion and inversion from positive charges, degrading the ability of associated termination structures to block high voltages. To improve the efficiency and stability of termination structures, second termination regions of the same dopant type as the substrate, more heavily doped than the substrate but more lightly doped than first termination regions, are positioned adjoining the first termination regions. The second termination regions raise the field threshold voltage where the surface is vulnerable and render the termination structure substantially insensitive to positive charges at the surface. The use of higher dopant concentration in the gap region without causing premature avalanche is facilitated by only creating second termination regions for regions lacking field plate protection.
摘要翻译：具有高电压端接结构的高电压半导体器件构造在轻掺杂衬底上。轻掺杂的p型衬底特别容易从正电荷中消耗和反转，降低了相关终端结构阻挡高电压的能力。为了提高端接结构的效率和稳定性，与衬底相同的掺杂剂类型的第二端接区域比衬底更重掺杂，但是比第一端接区域更轻掺杂的位置与第一端接区域相邻。第二终端区域提高了表面易受伤害的场阈值电压，并使端接结构对表面的正电荷基本上不敏感。通过仅为缺少场板保护的区域创建第二终止区域，便于促进间隙区域中较高掺杂剂浓度而不引起过早雪崩。

8. 发明授权

US5528058A IGBT device with platinum lifetime control and reduced gaw 失效
标题翻译： IGBT器件具有铂寿命控制和减少的gaw
公开(公告)号：US5528058A
公开(公告)日：1996-06-18
申请号：US329974
申请日：1994-10-13
申请人： Douglas A. Pike, Jr. , Dah W. Tsang , James M. Katana , Dumitru Sdrulla
发明人： Douglas A. Pike, Jr. , Dah W. Tsang , James M. Katana , Dumitru Sdrulla
IPC分类号： H01L21/033 , H01L21/22 , H01L21/266 , H01L21/3065 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/739 , H01L29/745 , H01L29/749 , H01L29/78 , H01L29/74 , H01L31/111
CPC分类号： H01L29/408 , H01L21/033 , H01L21/221 , H01L21/266 , H01L21/3065 , H01L29/0619 , H01L29/1095 , H01L29/41741 , H01L29/6634 , H01L29/7396 , H01L29/7455 , H01L29/749 , H01L29/7802 , H01L29/41766 , H01L29/66545
摘要： For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.3 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay. P+ doping beneath and marginally surrounding the gate pads and main gate bus negates breakdown conditions in widely spaced body regions and convex localities at the source finger end. Wide secondary gate buses parallel to the gate fingers have a P+ doped central stripe and transverse shorting bars spaced along their length. A non-polarizable PECVD passivation film of low phosphorus PSG and nitride or oxynitride or of oxynitride alone is made by controlling ionized gas residence time, silane partial pressure, and oxygen ratio during deposition, to minimize incorporation of Si--H into the film.
摘要翻译：对于IGBT，MCT等器件，衬底由P +，N +和N-层和PN扩散形成，以限定N层中的主体和源极区域以及上表面的MOS栅极通道。 N层的尺寸和掺杂（DIFFERENCE 1014 / cm3）以阻止反向偏置电压。 N +层厚度>20μm，掺杂低于DIFFERENCE 1017 / cm3，但高于N-掺杂，以增强输出阻抗，并降低高Vce条件下的增益。或者N +层形成为具有高（DIFFERENCE5μm）的高掺杂（> 1017 / cm3）层和厚（>20μm）DIFFERENCE 1016 / cm3掺杂的层。离子注入1013至1016 / cm2的铂剂量并扩散到硅中以实现寿命控制。栅极和源极触点以及主体和源极扩散具有互补锥形的数字化指状图案，以最小化电流拥挤和宽栅极总线以最小化信号延迟。在栅极焊盘和主栅极总线下面和边缘周围的P +掺杂不利于在源极端部处的宽间隔的体区域和凸起位置中的击穿条件。平行于栅极指的宽二级栅极总线具有P +掺杂的中心条和沿其长度间隔开的横向短路条。通过在沉积期间控制离子化的气体停留时间，硅烷分压和氧气比例来制备低磷PSG和氮化物或氧氮化物或氮氧化物或单独的氮氧化物的不可极化的PECVD钝化膜，以最小化Si-H到薄膜中的掺入。

9. 发明授权

US08674439B2 Low loss SiC MOSFET 有权
标题翻译：低损耗SiC MOSFET
公开(公告)号：US08674439B2
公开(公告)日：2014-03-18
申请号：US13195632
申请日：2011-08-01
申请人： Dumitru Sdrulla , Bruce Odekirk , Marc Vandenberg
发明人： Dumitru Sdrulla , Bruce Odekirk , Marc Vandenberg
IPC分类号： H01L29/78
CPC分类号： H01L29/66666 , H01L21/049 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/42368 , H01L29/66068 , H01L29/7395 , H01L29/7802
摘要： A Vertical Multiple Implanted Silicon Carbide Power MOSFET (VMIMOSFET) includes a first conductivity semiconductor substrate, a first conductivity semiconductor drift layer on the top of the substrate, a multitude of second conductivity layers implanted in the drift layer. The body layer is where the channel is formed. A first conductivity source layer is interspaced appropriately inside of the second conductivity layers. A gate oxide of a certain thickness and another oxide of a different thickness, a greater thickness than the gate oxide, placed in between the body layers but in such way that its shape does not distort the gate oxide in the channel. A charge compensated body layer of the second conductivity formed outside of the channel region and only at specific high electric field locations in the structure. The device and the manufacturing method deliver a power SiC MOSFET with increased frequency of operation and reduced switching losses.
摘要翻译：垂直多重注入碳化硅功率MOSFET（VMIMOSFET）包括第一导电半导体衬底，衬底顶部上的第一导电半导体漂移层，注入漂移层中的多个第二导电层。身体层是形成通道的地方。第一导电源层在第二导电层内适当地间隔开。具有一定厚度的栅极氧化物和不同厚度的另一种氧化物，比栅极氧化物更大的厚度，放置在主体层之间，但是使得其形状不使通道中的栅极氧化物变形。第二导电体的电荷补偿体层形成在沟道区域外部，并且仅在该结构中的特定高电场位置。该器件和制造方法提供功率SiC MOSFET，具有更高的工作频率和更低的开关损耗。

10. 发明授权

US08110888B2 Edge termination for high voltage semiconductor device 有权
标题翻译：高压半导体器件的边缘端接
公开(公告)号：US08110888B2
公开(公告)日：2012-02-07
申请号：US12206954
申请日：2008-09-09
申请人： Jinshu Zhang , Dumitru Sdrulla , Dah Wen Tsang
发明人： Jinshu Zhang , Dumitru Sdrulla , Dah Wen Tsang
IPC分类号： H01L23/58 , H01L21/765
CPC分类号： H01L29/66712 , H01L21/761 , H01L29/0619 , H01L29/0638 , H01L29/0878 , H01L29/404 , H01L29/7811
摘要： High voltage semiconductor devices with high-voltage termination structures are constructed on lightly doped substrates. Lightly doped p-type substrates are particularly prone to depletion and inversion from positive charges, degrading the ability of associated termination structures to block high voltages. To improve the efficiency and stability of termination structures, second termination regions of the same dopant type as the substrate, more heavily doped than the substrate but more lightly doped than first termination regions, are positioned adjoining the first termination regions. The second termination regions raise the field threshold voltage where the surface is vulnerable and render the termination structure substantially insensitive to positive charges at the surface. The use of higher dopant concentration in the gap region without causing premature avalanche is facilitated by only creating second termination regions for regions lacking field plate protection.
摘要翻译：具有高电压端接结构的高电压半导体器件构造在轻掺杂衬底上。轻掺杂的p型衬底特别容易从正电荷中消耗和反转，降低了相关终端结构阻挡高电压的能力。为了提高端接结构的效率和稳定性，与衬底相同的掺杂剂类型的第二端接区域比衬底更重掺杂，但是比第一端接区域更轻掺杂的位置与第一端接区域相邻。第二终端区域提高了表面易受伤害的场阈值电压，并使端接结构对表面的正电荷基本上不敏感。通过仅为缺少场板保护的区域创建第二终止区域，便于促进间隙区域中较高掺杂剂浓度而不引起过早雪崩。

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