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1. 发明申请

US20140204684A1 NONVOLATILE MEMORY DEVICES, MEMORY SYSTEMS AND RELATED CONTROL METHODS 有权
标题翻译：非易失性存储器件，存储器系统和相关控制方法
公开(公告)号：US20140204684A1
公开(公告)日：2014-07-24
申请号：US14153627
申请日：2014-01-13
申请人： DONGHUN KWAK , HYUN JUN YOON , DONGKYO SHIM
发明人： DONGHUN KWAK , HYUN JUN YOON , DONGKYO SHIM
IPC分类号： G11C7/10
CPC分类号： G11C7/22 , G11C7/10 , G11C7/1063 , G11C16/0483 , G11C16/26
摘要： A nonvolatile memory device includes a cell array including a plurality of cell strings extending on a substrate in a vertical direction, a page buffer connected to a plurality of bit lines and configured to store sensing data of the cell array in a sensing operation, a voltage generator configured to provide voltages to a plurality of word lines and the plurality of bit lines, and an input/output buffer configured to temporarily store the sensing data received in a data dump from the page buffer and to output the temporarily stored data to an external device. The nonvolatile memory device further includes control logic configured to set a status of the nonvolatile memory device to a ready state after the sensing data is dumped to the input/output buffer and before recovery of the cell array from a bias voltage of the sensing operation is complete.
摘要翻译：一种非易失性存储器件，包括一个单元阵列，该单元阵列包括在垂直方向上在基片上延伸的多个单元串，连接到多个位线的一个页缓冲器，并且被配置为在感测操作中存储该单元阵列的感测数据，发生器，其被配置为向多个字线和所述多个位线提供电压;以及输入/输出缓冲器，被配置为临时存储从所述页缓冲器接收的数据转储中的感测数据，并将所述临时存储的数据输出到外部设备。非易失性存储装置还包括控制逻辑，其被配置为在将感测数据转储到输入/输出缓冲器之后并且在从感测操作的偏置电压恢复单元阵列之前将非易失性存储器件的状态设置为就绪状态完成。

2. 发明申请

US20150049545A1 NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM COMPRISING SAME, AND METHOD OF PROGRAMMING SAME 有权
标题翻译：非易失性存储器件，包含其的存储器系统及其编程方法
公开(公告)号：US20150049545A1
公开(公告)日：2015-02-19
申请号：US14278743
申请日：2014-05-15
申请人： JONGHOO JO , HYUN JUN YOON , KITAE PARK , DONGKYO SHIM
发明人： JONGHOO JO , HYUN JUN YOON , KITAE PARK , DONGKYO SHIM
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/08 , G11C16/10
摘要： A method of programming a nonvolatile memory device comprises performing an N-th program loop based on state data stored in data latches according to a default state ordering, determining whether conversion of the default state ordering is required according to a predetermined criterion, as a consequence of determining that conversion of the default state ordering is required, converting all or part of the state data stored in the data latches from the default state ordering to another state ordering, and performing a (N+1)th program loop based on the converted state data.
摘要翻译：一种非易失性存储器件的编程方法包括：根据默认状态顺序，根据存储在数据锁存器中的状态数据执行第N个程序循环，确定是否需要根据预定标准转换默认状态排序，结果确定需要转换默认状态排序，将存储在数据锁存器中的全部或部分状态数据从默认状态排序转换到另一状态排序，以及基于转换的第（N + 1）个程序循环执行状态数据。

3. 发明申请

US20170200502A1 NONVOLATILE MEMORY DEVICE AND A METHOD OF READING THE SAME 审中-公开
公开(公告)号：US20170200502A1
公开(公告)日：2017-07-13
申请号：US15398014
申请日：2017-01-04
申请人： HYUN JUN YOON , JI-SANG LEE
发明人： HYUN JUN YOON , JI-SANG LEE
IPC分类号： G11C16/08 , G11C16/20 , G11C16/26
CPC分类号： G11C16/08 , G11C16/20 , G11C16/26 , G11C16/32
摘要： A nonvolatile memory device includes a memory cell array including a plurality of memory cells, an address decoder configured to be connected to the memory cells through a plurality of word lines and to provide select or unselect read voltages to the word lines, and a control logic configured to control the address decoder to perform a plurality of read sequences in a continuous read mode and to adjust a word line setup start point in at least one of the read sequences to be different than a word line setup start point in at least one of the other read sequences, wherein the word line setup start point is a time at which the select or unselect read voltages begin to be provided to the word lines.

4. 发明申请

US20140104955A1 PROGRAMMING NONVOLATILE MEMORY DEVICE USING PROGRAM VOLTAGE WITH VARIABLE OFFSET 有权
标题翻译：使用可变偏置的程序电压编程非易失性存储器件
公开(公告)号：US20140104955A1
公开(公告)日：2014-04-17
申请号：US13969651
申请日：2013-08-19
申请人： DONG-HUN KWAK , HYUN-WOOK PARK , HYUN JUN YOON , DOOHYUN KIM , KI-TAE PARK
发明人： DONG-HUN KWAK , HYUN-WOOK PARK , HYUN JUN YOON , DOOHYUN KIM , KI-TAE PARK
IPC分类号： G11C16/12
CPC分类号： G11C16/28 , G11C11/5628 , G11C16/00 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3454 , G11C16/3459 , G11C29/021 , G11C29/028 , G11C2029/0409 , H01L27/11556 , H01L27/1157 , H01L27/11582
摘要： A method of programming a nonvolatile memory device comprises applying at least one test program pulse to selected memory cells located in a scan read area, performing a scan read operation on the selected memory cells following application of the at least one test program pulse to detect at least one one-shot upper cell, calculating an offset voltage corresponding to a scan read region at which the scan read operation is performed, setting a program start bias using the offset voltage, and executing at least one program loop using the program start bias.
摘要翻译：一种对非易失性存储器件进行编程的方法包括将至少一个测试程序脉冲施加到位于扫描读取区域中的选定存储器单元，在施加至少一个测试程序脉冲之后对所选存储单元执行扫描读取操作，以在计算对应于执行扫描读取操作的扫描读取区域的偏移电压，使用偏移电压设置程序开始偏置，以及使用程序启动偏差执行至少一个程序循环。

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