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1. 发明授权

US09190495B2 Recessed channel array transistors, and semiconductor devices including a recessed channel array transistor 有权
标题翻译：嵌入式沟道阵列晶体管和包括凹陷沟道阵列晶体管的半导体器件
公开(公告)号：US09190495B2
公开(公告)日：2015-11-17
申请号：US12563473
申请日：2009-09-21
申请人： Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Jong-Ryeol Yoo , Jong-Hoon Kang
发明人： Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Jong-Ryeol Yoo , Jong-Hoon Kang
IPC分类号： H01L27/06 , H01L29/78 , H01L29/66 , H01L21/28 , H01L27/105 , H01L27/108 , H01L27/11 , H01L29/423 , H01L29/51 , H01L21/336 , H01L21/8234
CPC分类号： H01L29/66795 , H01L21/28211 , H01L21/823412 , H01L27/105 , H01L27/10876 , H01L27/10879 , H01L27/10894 , H01L27/11 , H01L29/4236 , H01L29/51 , H01L29/66621 , H01L29/7851
摘要： A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.
摘要翻译：凹陷通道阵列晶体管可以包括衬底，栅极氧化物层，栅极电极和源极/漏极区域。衬底可以具有有源区和隔离区。可以在活性区域中形成凹部。栅极氧化物层可以形成在凹部和基板上。栅极氧化物层可以包括在凹部的侧端和有源区的侧壁与凹部的侧表面上的第二部分之间的交叉处的第一部分。第一部分可以包括大于第二部分厚度的约70％的厚度。栅极电极可以形成在栅极氧化物层上。源极/漏极区域可以形成在衬底中。因此，凹陷通道阵列晶体管可能具有减小的漏电流和增加的导通电流。

2. 发明授权

US09140463B2 Indoor unit with power supply and power detection capabilities and method thereof and air conditioning system having the same 有权
标题翻译：具有电源和电力检测能力及其方法的室内单元和具有该室内单元的空调系统
公开(公告)号：US09140463B2
公开(公告)日：2015-09-22
申请号：US13067339
申请日：2011-05-25
申请人： Su Ho Jo , Kwan Joo Myoung , Awata Hiroshi , O Do Ryu
发明人： Su Ho Jo , Kwan Joo Myoung , Awata Hiroshi , O Do Ryu
IPC分类号： F24F11/00
CPC分类号： F24F11/0009 , F24F11/30 , F24F11/56 , Y10T307/696
摘要： An indoor unit performs a control operation to not supply power to a load device through a power/communication line simultaneously with other indoor units. An air conditioning system may includes an indoor unit including a microcomputer to output a power application signal to supply power to a load device through a power/communication line, and a duplicate power application prevention unit to interrupt the power application signal from the microcomputer when the power is simultaneously applied to the power/communication line by a different indoor unit, to prevent the power from being duplicately applied to the power/communication line.
摘要翻译：室内机进行与其他室内机同时通过电力/通信线路向负载装置供电的控制动作。空调系统可以包括：室内单元，其包括微型计算机，用于输出电力应用信号，以通过电力/通信线路向负载设备供电;以及复制电力应用防止单元，当所述电力应用信号通过不同的室内单元将电力同时施加到电力/通信线路，以防止电力复制地施加到电力/通信线路。

3. 发明授权

US08302433B2 Damper, washing machine with the same and control method thereof 有权
标题翻译：阻尼器，洗衣机具有相同的控制方法
公开(公告)号：US08302433B2
公开(公告)日：2012-11-06
申请号：US12588454
申请日：2009-10-15
申请人： Jeong Su Han , Ho Yoon , Jung Hyeon Kim , Hyen Young Choi , Sang Jun Lee , Jung Won Choi , O Do Ryu
发明人： Jeong Su Han , Ho Yoon , Jung Hyeon Kim , Hyen Young Choi , Sang Jun Lee , Jung Won Choi , O Do Ryu
IPC分类号： D06F29/00
CPC分类号： D06F39/003 , D06F37/203 , F16F7/09 , F16F9/3292 , F16F9/56 , F16F2230/08 , F16F2232/04
摘要： A damper including a cylinder, a piston inserted in the cylinder, a movable member disposed in the piston to be movable in the cylinder in a length direction of the cylinder, and a weight sensor mounted on an inner surface of the cylinder, facing an end of the piston, to perceive weight loaded on the piston through contact with the movable member. When applied to a washing machine, the damper is capable of perceiving accurate weight of the laundry supplied in the washing machine.
摘要翻译：一种阻尼器，包括：气缸，插入气缸中的活塞，设置在活塞中的可移动构件，以在气缸的长度方向上在气缸中移动;以及重量传感器，其安装在气缸的内表面上，以感知通过与活动件接触而装载在活塞上的重量。当应用于洗衣机时，阻尼器能够感知洗衣机中提供的衣物的精确重量。

4. 发明授权

US08252681B2 Methods of forming integrated circuit devices having electrically conductive layers therein with partially nitridated sidewalls 有权
标题翻译：形成其中具有部分氮化侧壁的导电层的集成电路器件的方法
公开(公告)号：US08252681B2
公开(公告)日：2012-08-28
申请号：US12536865
申请日：2009-08-06
申请人： Jeong-Do Ryu , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Dong-Chan Kim , Jong-Ryeol Yoo , Seong-Hoon Jeong , Jong-Hoon Kang
发明人： Jeong-Do Ryu , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Dong-Chan Kim , Jong-Ryeol Yoo , Seong-Hoon Jeong , Jong-Hoon Kang
IPC分类号： H01L21/44
CPC分类号： H01L21/28061 , H01L21/28247 , H01L21/3211 , H01L21/32137 , H01L21/32139 , H01L27/10873 , H01L27/11 , H01L27/1104
摘要： Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.
摘要翻译：形成集成电路器件的方法包括在衬底上形成含硅的导电层，并在导电层上形成掩模图案。使用掩模图案作为蚀刻掩模，选择性地蚀刻导电层以限定其上的第一侧壁。可以将导电层的第一侧壁暴露于氮等离子体，从而在第一侧壁上形成第一氮化硅层。然后再次选择性地蚀刻导电层以暴露其上没有第一氮化硅层的第二侧壁。在选择性蚀刻导电层的第二步骤期间，掩模图案可以再次用作蚀刻掩模。

5. 发明申请

US20100126191A1 Cooling system and method of controlling the same 审中-公开
标题翻译：冷却系统及其控制方法
公开(公告)号：US20100126191A1
公开(公告)日：2010-05-27
申请号：US12457807
申请日：2009-06-22
申请人： Jeong Su Han , Sang Jun Lee , Kook Jeong Seo , Ho Yoon , Jung Hyeon Kim , Hyen Young Choi , O Do Ryu
发明人： Jeong Su Han , Sang Jun Lee , Kook Jeong Seo , Ho Yoon , Jung Hyeon Kim , Hyen Young Choi , O Do Ryu
IPC分类号： F25D21/02 , F25D21/06
CPC分类号： F25D21/02 , F25B2700/111
摘要： An oscillatory wave generating unit and an oscillatory wave sensing unit are installed at both ends of a refrigerant pipe of an evaporator of the cooling system, an amount of frost formed on the refrigerant pipe is determined by comparing a wave form of an oscillatory wave generated from one end of the refrigerant through the oscillatory wave generating unit and a wave form of the oscillatory wave sensed by the other one end of the refrigerant through the oscillatory wave sensing unit, and whether or not a defrosting operation is performed is determined by a result of the determination. The cooling system increases the accuracy in sensing the amount of the frost formed on the evaporator of a refrigerator, a Kimchi refrigerator, or an air conditioner, and respectively starts and ends the defrosting operation at proper points of time, thus enhancing a heat-exchanging performance and increasing energy efficiency.
摘要翻译：在冷却系统的蒸发器的制冷剂管的两端安装振荡波产生单元和振荡波感测单元，通过比较从制冷剂管道的蒸发器产生的振荡波的波形，通过振荡波产生单元的制冷剂的一端和通过振荡波感测单元由制冷剂的另一端感测的振荡波的波形，以及是否执行除霜操作由以下结果确定：决心。冷却系统提高了感测冰箱，泡菜冰箱或空调器的蒸发器上形成的霜的量的精度，并分别在合适的时间点开始和结束除霜操作，从而增强了热交换性能和提高能源效率。

6. 发明授权

US07697336B2 Non-volatile memory device and method of operating the same 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US07697336B2
公开(公告)日：2010-04-13
申请号：US11903482
申请日：2007-09-21
申请人： Chang-Min Jeon , Hee-Seog Jeon , Hyun-Khe Yoo , Sung-Gon Choi , Bo-Young Seo , Ji-Do Ryu
发明人： Chang-Min Jeon , Hee-Seog Jeon , Hyun-Khe Yoo , Sung-Gon Choi , Bo-Young Seo , Ji-Do Ryu
IPC分类号： G11C11/34
CPC分类号： G11C16/0433 , H01L27/115 , H01L27/11524
摘要： The present invention is directed to a non-volatile memory device and a method of operating the same. The non-volatile memory device includes a first transistor connected to an nth bitline and a second transistor connected to an (n+1)th bitline. The first transistor and the second transistor are serially coupled between the nth bitline and the (n+1)th bitline. The non-volatile memory device may include a 2-transistor 1-bit unit cell where a drain region and a source region of a memory cell have the same or similar structure. Since a cell array of a non-volatile memory device according to the invention may include a 2-transistor 2-bit unit cell, storage capacity of the non-volatile memory device may be doubled.
摘要翻译：本发明涉及一种非易失性存储器件及其操作方法。非易失性存储器件包括连接到第n位线的第一晶体管和连接到第（n + 1）位线的第二晶体管。第一晶体管和第二晶体管串联耦合在第n位线和第（n + 1）位线之间。非易失性存储器件可以包括2晶体管1位单元，其中存储单元的漏极区域和源极区域具有相同或相似的结构。由于根据本发明的非易失性存储器件的单元阵列可以包括2-晶体管2位单位单元，所以非易失性存储器件的存储容量可以加倍。

7. 发明授权

US07696561B2 Non-volatile memory device, method of manufacturing the same and method of operating the same 失效
标题翻译：非易失性存储器件，其制造方法及其操作方法
公开(公告)号：US07696561B2
公开(公告)日：2010-04-13
申请号：US11870762
申请日：2007-10-11
申请人： Hyun-Khe Yoo , Jeong-Uk Han , Hee-Seog Jeon , Sung-Gon Choi , Bo-Young Seo , Chang-Min Jeon , Ji-Do Ryu
发明人： Hyun-Khe Yoo , Jeong-Uk Han , Hee-Seog Jeon , Sung-Gon Choi , Bo-Young Seo , Chang-Min Jeon , Ji-Do Ryu
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A non-volatile memory device includes a first sensing line, a first word line, a depletion channel region, and impurity regions. The first sensing line and the first word line are formed adjacent to each other in parallel on a substrate. The first sensing line and the first word line have a tunnel oxide layer, a first conductive pattern, a dielectric layer pattern and a second conductive pattern sequentially stacked on the substrate. The depletion channel region is formed at an upper portion of the substrate under the first sensing line. The impurity regions are formed at upper portions of the substrate exposed by the first sensing line and the first word line.
摘要翻译：非易失性存储器件包括第一感测线，第一字线，耗尽沟道区和杂质区。第一感测线和第一字线在基板上彼此平行地相邻地形成。第一感测线和第一字线具有依次层叠在衬底上的隧道氧化物层，第一导电图案，电介质层图案和第二导电图案。耗尽沟道区形成在第一感测线下方的衬底的上部。在由第一感测线和第一字线露出的衬底的上部形成杂质区。

8. 发明授权

US07512003B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US07512003B2
公开(公告)日：2009-03-31
申请号：US11789003
申请日：2007-04-23
申请人： Hyun-Khe Yoo , Ji-Do Ryu , Bo-Young Seo , Chang-Min Jeon , Hee-Seog Jeon , Sung-Gon Choi , Jeong-Uk Han
发明人： Hyun-Khe Yoo , Ji-Do Ryu , Bo-Young Seo , Chang-Min Jeon , Hee-Seog Jeon , Sung-Gon Choi , Jeong-Uk Han
IPC分类号： G11C11/34
CPC分类号： G11C16/0433 , G11C7/18 , G11C16/24 , G11C2207/002
摘要： A non-volatile memory device includes a memory cell block, a first switching block, and a second switching block. A plurality of memory cells are arranged in the memory cell block and each of the memory cells includes a memory transistor having a floating gate and a control gate and is connected to a local bit line and includes a selection transistor connected to the memory transistor in series that is connected to a source line. The first switching block selectively connects a global bit line to the local bit line and the second switching block controls the memory cells in the memory cell block in units of a predetermined number of bits. The first switching block includes at least two switching devices connected in parallel between the global bit line and the local bit line.
摘要翻译：非易失性存储器件包括存储器单元块，第一切换块和第二切换块。多个存储单元布置在存储单元块中，并且每个存储单元包括具有浮置栅极和控制栅极的存储晶体管，并连接到局部位线，并且包括串联连接到存储晶体管的选择晶体管它连接到源线。第一切换块选择性地将全局位线连接到本地位线，而第二切换块以预定位数为单位来控制存储单元块中的存储单元。第一切换块包括在全局位线和局部位线之间并联连接的至少两个开关器件。

9. 发明申请

US20080253190A1 Non-volatile memory device and method of operating the same 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20080253190A1
公开(公告)日：2008-10-16
申请号：US11903482
申请日：2007-09-21
申请人： Chang-Min Jeon , Hee-Seog Jeon , Hyun-Khe Yoo , Sung-Gon Choi , Bo-Young Seo , Ji-Do Ryu
发明人： Chang-Min Jeon , Hee-Seog Jeon , Hyun-Khe Yoo , Sung-Gon Choi , Bo-Young Seo , Ji-Do Ryu
IPC分类号： G11C16/06 , H01L29/788
CPC分类号： G11C16/0433 , H01L27/115 , H01L27/11524
摘要： The present invention is directed to a non-volatile memory device and a method of operating the same. The non-volatile memory device includes a first transistor connected to an nth bitline and a second transistor connected to an (n+1)th bitline. The first transistor and the second transistor are serially coupled between the nth bitline and the (n+1)th bitline. The non-volatile memory device may include a 2-transistor 1-bit unit cell where a drain region and a source region of a memory cell have the same or similar structure. Since a cell array of a non-volatile memory device according to the invention may include a 2-transistor 2-bit unit cell, storage capacity of the non-volatile memory device may be doubled.
摘要翻译：本发明涉及一种非易失性存储器件及其操作方法。非易失性存储器件包括连接到第n位线的第一晶体管和连接到第（n + 1）位线的第二晶体管。第一晶体管和第二晶体管串联耦合在第n位线和第（n + 1）位线之间。非易失性存储器件可以包括2晶体管1位单元，其中存储单元的漏极区域和源极区域具有相同或相似的结构。由于根据本发明的非易失性存储器件的单元阵列可以包括2-晶体管2位单位单元，所以非易失性存储器件的存储容量可以加倍。

10. 发明申请

US20080055206A1 Driving method of a display 有权
标题翻译：显示器的驱动方法
公开(公告)号：US20080055206A1
公开(公告)日：2008-03-06
申请号：US11892478
申请日：2007-08-23
申请人： Do Ryu , Do Kim
发明人： Do Ryu , Do Kim
IPC分类号： G09G3/30
CPC分类号： G09G3/2022 , G09G3/3258 , G09G3/3266 , G09G2310/0213 , G09G2310/0218 , G09G2310/0278 , G09G2320/0266
摘要： In a method for driving a display, one frame may be divided into more sub frames than a number of bits of data. A time period of the one frame may be divided into a number of periods corresponding to a number of scan lines multiplied by the number of sub frames. A start position of the sub frames may be set based on a bit weight of the data so that gradations are linearly expressed. Remainders of the sub frames may be obtained by dividing the start position of the sub frames by the number of sub frames. A line number of a scan line to which a scan signal is supplied may be obtained based on the time period of the one frame, the start position of the sub frames, and the number of the sub frames.
摘要翻译：在用于驱动显示器的方法中，一帧可以被划分成比数据位数更多的子帧。一帧的时间段可以被划分为与扫描线的数量相乘的多个周期乘以子帧的数量。可以基于数据的位权重来设置子帧的开始位置，使得等级线性地表示。可以通过将子帧的开始位置除以子帧的数量来获得子帧的剩余。可以基于一帧的时间段，子帧的开始位置和子帧的数量来获得提供扫描信号的扫描线的行号。

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