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1. 发明申请

US20060024869A1 Gate material for semiconductor device fabrication 有权
公开(公告)号：US20060024869A1
公开(公告)日：2006-02-02
申请号：US11237175
申请日：2005-09-28
申请人： Anthony Lochtefeld , Dimitri Antoniadis , Matthew Currie
发明人： Anthony Lochtefeld , Dimitri Antoniadis , Matthew Currie
IPC分类号： H01L21/84
CPC分类号： H01L29/7842 , H01L21/28079 , H01L21/28097 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823842 , H01L29/1054 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/66583 , H01L29/78654 , Y10S438/938
摘要： In forming an electronic device, a semiconductor layer is pre-doped and a dopant distribution anneal is performed prior to gate definition. Alternatively, the gate is formed from a metal. Subsequently formed shallow sources and drains, therefore, are not affected by the gate annealing step.

2. 发明申请

US20050136624A1 Method for semiconductor device fabrication 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20050136624A1
公开(公告)日：2005-06-23
申请号：US11028248
申请日：2005-01-03
申请人： Zhiyuan Cheng , Eugene Fitzgerald , Dimitri Antoniadis
发明人： Zhiyuan Cheng , Eugene Fitzgerald , Dimitri Antoniadis
IPC分类号： H01L21/20 , H01L21/306 , H01L21/762 , H01L29/06 , C30B1/00 , H01L21/302 , H01L21/36 , H01L21/461 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L21/76256 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/02664 , H01L21/30608
摘要： A method of fabricating a semiconductor structure. According to one aspect of the invention, on a first semiconductor substrate, a first compositionally graded Si1-xGex buffer is deposited where the Ge composition x is increasing from about zero to a value less than about 20%. Then a first etch-stop Si1-yGey layer is deposited where the Ge composition y is larger than about 20% so that the layer is an effective etch-stop. A second etch-stop layer of strained Si is then grown. The deposited layer is bonded to a second substrate. After that the first substrate is removed to release said first etch-stop S1-yGey layer. The remaining structure is then removed in another step to release the second etch-stop layer. According to another aspect of the invention, a semiconductor structure is provided. The structure has a layer in which semiconductor devices are to be formed. The semiconductor structure includes a substrate, an insulating layer, a relaxed SiGe layer where the Ge composition is larger than approximately 15%, and a device layer selected from a group consisting of, but not limited to, strained-Siy relaxed Si1-yGey layer, strained Si1-zGey layer, Ge, GaAs, III-V materials, and II-VI materials, where Ge compositions y and z are values between 0 and 1.
摘要翻译：一种制造半导体结构的方法。根据本发明的一个方面，在第一半导体衬底上沉积第一组分梯度的Si 1-x N Ge x N x缓冲层，其中Ge组合物x从约零到小于约20％的值。然后沉积第一蚀刻停止Si 1-y Ge层，其中Ge组分y大于约20％，使得该层是有效的蚀刻停止。然后生长第二蚀刻停止层的应变Si。沉积层结合到第二衬底。之后，移除第一衬底以释放所述第一蚀刻停止层1-y层。然后在另一步骤中除去剩余的结构以释放第二蚀刻停止层。根据本发明的另一方面，提供一种半导体结构。该结构具有要形成半导体器件的层。半导体结构包括衬底，绝缘层，Ge组分大于约15％的弛豫SiGe层，以及选自但不限于应变Si Si层的器件层， Si 1 Y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y ，GaAs，III-V材料和II-VI材料，其中Ge组分y和z是0和1之间的值。

3. 发明申请

US20050009288A1 Process for producing semiconductor article using graded epitaxial growth 审中-公开
标题翻译：使用分级外延生长制造半导体产品的方法
公开(公告)号：US20050009288A1
公开(公告)日：2005-01-13
申请号：US10802186
申请日：2004-03-17
申请人： Zhi-Yuan Cheng , Eugene Fitzgerald , Dimitri Antoniadis , Judy Hoyt
发明人： Zhi-Yuan Cheng , Eugene Fitzgerald , Dimitri Antoniadis , Judy Hoyt
IPC分类号： H01L21/205 , H01L21/02 , H01L21/20 , H01L21/762 , H01L27/12 , H01L21/00 , C30B1/00 , H01L21/46 , H01L21/84
CPC分类号： H01L21/76254 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/0251 , H01L21/02521 , H01L21/02532 , H01L21/02546 , Y10S438/933
摘要： A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1-xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1-yGey layer, a thin strained Si1-zGez layer and another relaxed Si1-yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1-yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1-yGey layer remains on the second substrate. In another exemplary embodiment, a graded SixGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth. The relaxed GaAs layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the hydrogen ion rich layer, such that the upper portion of relaxed GaAs layer remains on the second substrate.
摘要翻译：一种制造单晶半导体层的方法。在示例性实施例中，分级的Si1-xGex（x从0增加到y）沉积在第一硅衬底上，随后沉积弛豫的Si1-yGey层，薄的应变Si1-zGez层和另一个弛豫的Si1-yGey 层。然后将氢离子引入应变SizGez层。松弛的Si1-yGey层与第二氧化基底结合。退火处理在接合的Si层处分离结合对，使得第二弛豫Si1-yGey层保留在第二基板上。在另一个示例性实施例中，分级的SixGex沉积在第一硅衬底上，其中Ge浓度x从0增加到1.然后在弛豫的Ge缓冲器上沉积弛豫的GaAs层。由于GaAs的晶格常数接近于Ge，所以GaAs具有高质量和有限的位错缺陷。在所选择的深度处将氢离子引入到松弛的GaAs层中。松弛的GaAs层结合到第二氧化衬底上。退火处理在氢离子富集层处分离结合对，使得松弛的GaAs层的上部保留在第二基板上。

4. 发明授权

US07390701B2 Method of forming a digitalized semiconductor structure 失效
标题翻译：形成数字化半导体结构的方法
公开(公告)号：US07390701B2
公开(公告)日：2008-06-24
申请号：US11087781
申请日：2005-03-23
申请人： Zhiyuan Cheng , Eugene A. Fitzgerald , Dimitri Antoniadis
发明人： Zhiyuan Cheng , Eugene A. Fitzgerald , Dimitri Antoniadis
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L29/66628 , H01L29/66795 , H01L29/7842 , H01L29/78687
摘要： A multiple-gate FET structure includes a semiconductor substrate. A gate region is formed on the semiconductor substrate. The gate region comprises a gate portion and a channel portion. The gate portion has at least two opposite vertical surfaces adjacent to the channel portion. A source region abuts the gate region at one end, and a drain diffusion region abuts the gate region at the other end.
摘要翻译：多栅极FET结构包括半导体衬底。在半导体衬底上形成栅区。栅极区域包括栅极部分和沟道部分。栅极部分具有与通道部分相邻的至少两个相对的垂直表面。源极区域在一端邻接栅极区域，漏极扩散区域在另一端邻接栅极区域。

5. 发明授权

US06991972B2 Gate material for semiconductor device fabrication 有权
标题翻译：用于半导体器件制造的栅极材料
公开(公告)号：US06991972B2
公开(公告)日：2006-01-31
申请号：US10691007
申请日：2003-10-22
申请人： Anthony J. Lochtefeld , Dimitri Antoniadis , Matthew T. Currie
发明人： Anthony J. Lochtefeld , Dimitri Antoniadis , Matthew T. Currie
IPC分类号： H01L21/00 , H01L27/01
CPC分类号： H01L29/7842 , H01L21/28079 , H01L21/28097 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823842 , H01L29/1054 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/66583 , H01L29/78654 , Y10S438/938
摘要： In forming an electronic device, a semiconductor layer is pre-doped and a dopant distribution anneal is performed prior to gate definition. Alternatively, the gate is formed from a metal. Subsequently formed shallow sources and drains, therefore, are not affected by the gate annealing step.
摘要翻译：在形成电子器件时，半导体层是预掺杂的，并且在栅极定义之前执行掺杂剂分布退火。或者，栅极由金属形成。因此，随后形成的浅源和漏极不受栅极退火步骤的影响。

6. 发明申请

US20050274978A1 Single metal gate material CMOS using strained si-silicon germanium heterojunction layered substrate 审中-公开
标题翻译：单金属栅极材料CMOS采用应变Si硅锗异质结层叠衬底
公开(公告)号：US20050274978A1
公开(公告)日：2005-12-15
申请号：US11138951
申请日：2005-05-26
申请人： Dimitri Antoniadis , Judy Hoyt , Jongwan Jung , Shaofeng Yu
发明人： Dimitri Antoniadis , Judy Hoyt , Jongwan Jung , Shaofeng Yu
IPC分类号： H01L21/8238 , H01L29/10 , H01L29/49 , H01L29/78 , H01L31/0328
CPC分类号： H01L21/823807 , H01L21/823828 , H01L29/1054 , H01L29/4966 , H01L29/78
摘要： Strained Si/strained SiGe dual-channel layer substrate provides mobility advantage and when used as a CMOS substrate enables single workfunction metal-gate electrode technology. A single metal electrode with workfunction of 4.5 eV produces near ideal CMOS performance on a dual-channel layer substrate that consists sequentially of a silicon wafer, an epitaxially grown 30% Ge relaxed SiGe layer, a compressively strained 60% Ge layer, and a tensile-strained Si cap layer.
摘要翻译：应变Si /应变SiGe双沟道层衬底提供了移动优势，并且当用作CMOS衬底时，可实现单功能金属栅电极技术。具有4.5eV功函数的单个金属电极在双通道层衬底上产生接近理想的CMOS性能，其依次由硅晶片，外延生长的30％Ge弛豫SiGe层，压缩应变的60％Ge层和拉伸有限硅层。

7. 发明授权

US07304336B2 FinFET structure and method to make the same 有权
标题翻译： FinFET结构和方法制作相同
公开(公告)号：US07304336B2
公开(公告)日：2007-12-04
申请号：US10778953
申请日：2004-02-13
申请人： Zhiyuan Cheng , Eugene A. Fitzgerald , Dimitri Antoniadis
发明人： Zhiyuan Cheng , Eugene A. Fitzgerald , Dimitri Antoniadis
IPC分类号： H01L29/76 , H01L29/32
CPC分类号： H01L29/785 , H01L29/66628 , H01L29/66795 , H01L29/7842 , H01L29/78687
摘要： A multiple-gate FET structure includes a semiconductor substrate. A gate region is formed on the semiconductor substrate. The gate region comprises a gate portion and a channel portion. The gate portion has at least two opposite vertical surfaces adjacent to the channel portion. A source region abuts the gate region at one end, and a drain diffusion region abuts the gate region at the other end.
摘要翻译：多栅极FET结构包括半导体衬底。在半导体衬底上形成栅区。栅极区域包括栅极部分和沟道部分。栅极部分具有与通道部分相邻的至少两个相对的垂直表面。源极区域在一端邻接栅极区域，漏极扩散区域在另一端邻接栅极区域。

8. 发明授权

US07074655B2 Gate material for semiconductor device fabrication 有权
公开(公告)号：US07074655B2
公开(公告)日：2006-07-11
申请号：US11237175
申请日：2005-09-28
申请人： Anthony J. Lochtefeld , Dimitri Antoniadis , Matthew T. Currie
发明人： Anthony J. Lochtefeld , Dimitri Antoniadis , Matthew T. Currie
IPC分类号： H01L21/00 , H01L27/01
CPC分类号： H01L29/7842 , H01L21/28079 , H01L21/28097 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823842 , H01L29/1054 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/66583 , H01L29/78654 , Y10S438/938
摘要： In forming an electronic device, a semiconductor layer is pre-doped and a dopant distribution anneal is performed prior to gate definition. Alternatively, the gate is formed from a metal. Subsequently formed shallow sources and drains, therefore, are not affected by the gate annealing step.

9. 发明申请

US20050202604A1 Integrated semiconductor device and method to make same 失效
标题翻译：集成半导体器件及其制作方法
公开(公告)号：US20050202604A1
公开(公告)日：2005-09-15
申请号：US11087781
申请日：2005-03-23
申请人： Zhiyuan Cheng , Eugene Fitzgerald , Dimitri Antoniadis
发明人： Zhiyuan Cheng , Eugene Fitzgerald , Dimitri Antoniadis
IPC分类号： H01L21/336 , H01L29/786 , H01L29/10
CPC分类号： H01L29/785 , H01L29/66628 , H01L29/66795 , H01L29/7842 , H01L29/78687
摘要： A multiple-gate FET structure includes a semiconductor substrate. A gate region is formed on the semiconductor substrate. The gate region comprises a gate portion and a channel portion. The gate portion has at least two opposite vertical surfaces adjacent to the channel portion. A source region abuts the gate region at one end, and a drain diffusion region abuts the gate region at the other end.
摘要翻译：多栅极FET结构包括半导体衬底。在半导体衬底上形成栅区。栅极区域包括栅极部分和沟道部分。栅极部分具有与通道部分相邻的至少两个相对的垂直表面。源极区域在一端邻接栅极区域，而漏极扩散区域在另一端邻接栅极区域。

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