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    • 5. 发明授权
    • Reconfigurable bus
    • 可重构总线
    • US4933845A
    • 1990-06-12
    • US93200
    • 1987-09-04
    • Dennis F. Hayes
    • Dennis F. Hayes
    • G06F13/40G06F15/177
    • G06F13/40G06F15/177
    • In a system having a first computer with a first processor, a reconfigurable bus for coupling the first processor to a first type of device in one configuration and to a second type of device in another configuration is accomplished using a bus coupled to the first processor and having at least a plurality of data and address lines and plurality of configuration lines, a device for detecting the assertion of a bit on one of the configuration lines, assertion indicating that a first type of device requiring an I/O bus is attached and nonassertion that a memory is attached and registers coupled to configuration lines to receive and store binary information on bus for one configuration and to receive an input on at least one of the lines and provide an output at least another of the lines in the other configuration.
    • 在具有具有第一处理器的第一计算机的系统中,使用耦合到第一处理器的总线来实现用于将第一处理器与一个配置中的第一类型的设备耦合到另一配置中的第二类型的设备的可重新配置总线,以及 具有至少多个数据和地址线和多个配置线,用于检测在其中一个配置线上的位的断言的设备,指示附加了需要I / O总线的第一类型的设备的断言,并且将非消除 附加存储器并且耦合到配置线的寄存器,以接收和存储用于一个配置的总线上的二进制信息,并且在至少一个线路上接收输入,并在另一配置中提供至少另一个线路的输出。