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1. 发明申请

US20130007418A1 FLUSH OPERATIONS IN A PROCESSOR 有权
标题翻译：处理器中的冲洗操作
公开(公告)号：US20130007418A1
公开(公告)日：2013-01-03
申请号：US13174293
申请日：2011-06-30
申请人： Jay E. Fleischman , Emil Talpes , Debjit DasSarma
发明人： Jay E. Fleischman , Emil Talpes , Debjit DasSarma
IPC分类号： G06F9/30
CPC分类号： G06F9/3865
摘要： Methods and apparatuses are provided for flush operations in a processor. The apparatus comprises an out-of-order execution unit for processing instructions issued in-order from an instruction decoder for first and second threads and being configured to identify an errored instruction in a first thread. A retire unit includes a retire queue for receiving completed instructions from the out-of-order execution unit, the retire unit being configured retire older in-order first thread instructions until the errored instruction would be the next instruction to be retired, and then flushing the errored instruction and all later in-order first thread instructions from the retire queue. The method comprises determining that an errored instruction is being processed by an out-of-order execution unit of a processor and continuing to process to completion instructions earlier in-order from the errored instruction until the completion of the errored instruction. Following completion of the errored instruction, it is flushed along with all instructions later in-order than the errored instruction to recover the processor to a pre-error state.
摘要翻译：为处理器中的冲洗操作提供了方法和装置。该装置包括用于处理从第一和第二线程的指令解码器按顺序发出的指令的无序执行单元，并且被配置为识别第一线程中的错误指令。退休单元包括用于从无序执行单元接收完成的指令的退出队列，所述退休单元被配置为退出旧的有序第一线程指令，直到错误的指令将是下一个待退出的指令，然后冲洗错误的指令和所有后续排序的第一线程指令从退出队列。所述方法包括：确定处理器的无序执行单元正在处理错误指令，并且继续处理从错误指令到故障指令完成之前的先前完成指令。完成错误指令之后，随着所有指令的刷新顺序都会比错误的指令进行刷新，以将处理器恢复到预错误状态。

2. 发明授权

US07836278B2 Three operand instruction extension for X86 architecture 有权
标题翻译： X86架构的三个操作指令扩展
公开(公告)号：US07836278B2
公开(公告)日：2010-11-16
申请号：US11954623
申请日：2007-12-12
申请人： Ranganathan Sudhakar , Michael Frank , Debjit Dassarma
发明人： Ranganathan Sudhakar , Michael Frank , Debjit Dassarma
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F9/30138 , G06F9/3016 , G06F9/30167 , G06F9/30185
摘要： A method and apparatus are contemplated for increasing the number of available instructions in an instruction set architecture. The new instructions extend the number of general-purpose registers and include three or more operands. A combination of an escape code field, an opcode field, an operation configuration field and an operation size field determines a unique new instruction operation. A source operand extension field includes bits to be combined with other fields in order to extend the number of source operand values for general-purpose registers.
摘要翻译：预期方法和装置用于增加指令集架构中可用指令的数量。新指令扩展通用寄存器的数量，并包括三个或更多个操作数。转义码字段，操作码字段，操作配置字段和操作大小字段的组合决定了唯一的新指令操作。源操作数扩展字段包括要与其他字段组合的位，以便扩展通用寄存器的源操作数值的数量。

3. 发明授权

US08838664B2 Methods and apparatus for compressing partial products during a fused multiply-and-accumulate (FMAC) operation on operands having a packed-single-precision format 有权
标题翻译：在融合乘法和累加（FMAC）操作期间对具有打包单精度格式的操作数压缩部分乘积的方法和装置
公开(公告)号：US08838664B2
公开(公告)日：2014-09-16
申请号：US13172590
申请日：2011-06-29
申请人： David Oliver , Debjit Dassarma , Hanbing Liu , Scott Hilker
发明人： David Oliver , Debjit Dassarma , Hanbing Liu , Scott Hilker
IPC分类号： G06F7/38 , G06F7/52 , G06F7/483 , G06F7/544
CPC分类号： G06F7/483 , G06F7/5443
摘要： The disclosed embodiments relate to methods and apparatus for accurately, efficiently and quickly executing a fused multiply-and-accumulate instruction with respect to floating-point operands that have packed-single-precision format. The disclosed embodiments can speed up computation of a high-part of a result during a fused multiply-and-accumulate operation so that cycle delay can be reduced and so that power consumption can be reduced.
摘要翻译：所公开的实施例涉及用于相对于具有打包单精度格式的浮点操作数精确，有效和快速地执行融合乘法和累加指令的方法和装置。所公开的实施例可以在融合的乘法和累加操作期间加速结果的高部分的计算，从而可以减少周期延迟，从而可以降低功耗。

4. 发明申请

US20090031116A1 THREE OPERAND INSTRUCTION EXTENSION FOR X86 ARCHITECTURE 有权
标题翻译： X86架构的三个操作指导扩展
公开(公告)号：US20090031116A1
公开(公告)日：2009-01-29
申请号：US11954623
申请日：2007-12-12
申请人： Ranganathan Sudhakar , Michael Frank , Debjit Dassarma
发明人： Ranganathan Sudhakar , Michael Frank , Debjit Dassarma
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F9/30138 , G06F9/3016 , G06F9/30167 , G06F9/30185
摘要： A method and apparatus are contemplated for increasing the number of available instructions in an instruction set architecture. The new instructions extend the number of general-purpose registers and include three or more operands. A combination of an escape code field, an opcode field, an operation configuration field and an operation size field determines a unique new instruction operation. A source operand extension field includes bits to be combined with other fields in order to extend the number of source operand values for general-purpose registers.
摘要翻译：预期方法和装置用于增加指令集架构中可用指令的数量。新指令扩展通用寄存器的数量，并包括三个或更多个操作数。转义码字段，操作码字段，操作配置字段和操作大小字段的组合决定了唯一的新指令操作。源操作数扩展字段包括要与其他字段组合的位，以便扩展通用寄存器的源操作数值的数量。

5. 发明申请

US20130007075A1 METHODS AND APPARATUS FOR COMPRESSING PARTIAL PRODUCTS DURING A FUSED MULTIPLY-AND-ACCUMULATE (FMAC) OPERATION ON OPERANDS HAVING A PACKED-SINGLE-PRECISION FORMAT 有权
标题翻译：在具有包装单精度格式的操作中，用于压缩多重和累积（FMAC）操作的部分产品的方法和装置
公开(公告)号：US20130007075A1
公开(公告)日：2013-01-03
申请号：US13172590
申请日：2011-06-29
申请人： David Oliver , Debjit Dassarma , Hanbing Liu , Scott Hilker
发明人： David Oliver , Debjit Dassarma , Hanbing Liu , Scott Hilker
IPC分类号： G06F17/10 , G06F7/487
CPC分类号： G06F7/483 , G06F7/5443
摘要： The disclosed embodiments relate to methods and apparatus for accurately, efficiently and quickly executing a fused multiply-and-accumulate instruction with respect to floating-point operands that have packed-single-precision format. The disclosed embodiments can speed up computation of a high-part of a result during a fused multiply-and-accumulate operation so that cycle delay can be reduced and so that power consumption can be reduced.
摘要翻译：所公开的实施例涉及用于相对于具有打包单精度格式的浮点操作数精确，有效和快速地执行融合乘法和累加指令的方法和装置。所公开的实施例可以在融合的乘法和累加操作期间加速结果的高部分的计算，从而可以减少周期延迟，从而可以降低功耗。

6. 发明授权

US09268575B2 Flush operations in a processor 有权
标题翻译：在处理器中进行冲洗操作
公开(公告)号：US09268575B2
公开(公告)日：2016-02-23
申请号：US13174293
申请日：2011-06-30
申请人： Jay E. Fleischman , Emil Talpes , Debjit DasSarma
发明人： Jay E. Fleischman , Emil Talpes , Debjit DasSarma
IPC分类号： G06F9/38
CPC分类号： G06F9/3865
摘要： Methods and apparatuses are provided for flush operations in a processor. The apparatus comprises an out-of-order execution unit for processing instructions issued in-order from an instruction decoder for first and second threads and being configured to identify an errored instruction in a first thread. A retire unit includes a retire queue for receiving completed instructions from the out-of-order execution unit, the retire unit being configured retire older in-order first thread instructions until the errored instruction would be the next instruction to be retired, and then flushing the errored instruction and all later in-order first thread instructions from the retire queue. The method comprises determining that an errored instruction is being processed by an out-of-order execution unit of a processor and continuing to process to completion instructions earlier in-order from the errored instruction until the completion of the errored instruction. Following completion of the errored instruction, it is flushed along with all instructions later in-order than the errored instruction to recover the processor to a pre-error state.
摘要翻译：为处理器中的冲洗操作提供了方法和装置。该装置包括用于处理从第一和第二线程的指令解码器按顺序发出的指令的无序执行单元，并且被配置为识别第一线程中的错误指令。退休单元包括用于从无序执行单元接收完成的指令的退出队列，退休单元被配置为退出较旧的有序第一线程指令，直到错误的指令将是下一个要退出的指令，然后冲洗错误的指令和所有后续排序的第一线程指令从退出队列。所述方法包括：确定处理器的无序执行单元正在处理错误指令，并且继续处理从错误指令到故障指令完成之前的先前完成指令。完成错误指令之后，随着所有指令的刷新顺序都会比错误的指令进行刷新，以将处理器恢复到预错误状态。

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