专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09597495B2 Locating a neural prosthesis using impedance and electrode height 有权
公开(公告)号：US09597495B2
公开(公告)日：2017-03-21
申请号：US13452300
申请日：2012-04-20
申请人： Robert J. Greenberg , Jone Fine , Arup Roy , Matthew J. McMahon , Mark S. Humayun , James David Welland , Alan M. Horsager , Dao Min Zhou , Amy Hines , Sumit Yadav , Rongqing Dai
发明人： Robert J. Greenberg , Jone Fine , Arup Roy , Matthew J. McMahon , Mark S. Humayun , James David Welland , Alan M. Horsager , Dao Min Zhou , Amy Hines , Sumit Yadav , Rongqing Dai
IPC分类号： A61N1/05 , A61N1/36 , A61N1/372
CPC分类号： A61N1/0543 , A61N1/36046 , A61N1/37247
摘要： The invention is a method of identifying a preferred location for an electrode array to the neural characteristics of an individual subject. The response to electrical neural stimulation varies from subject to subject and array location to array location. Measure of impedance may be used to predict the electrode height from the neural tissue and, thereby, predict the preferred location. Alternatively, electrode height may be measured directly to predict the preferred location.

2. 发明申请

US20120203293A1 Locating a Neural Prosthesis using Impedance and Electrode Height 有权
标题翻译：使用阻抗和电极高度定位神经假体
公开(公告)号：US20120203293A1
公开(公告)日：2012-08-09
申请号：US13452300
申请日：2012-04-20
申请人： Robert J. Greenberg , Jone Fine , Arup Roy , Matthew J. McMahon , Mark S. Humayun , James David Welland , Alan M. Horsager , Dao Min Zhou , Amy Hines , Sumit Yadav , Rongqing Dai
发明人： Robert J. Greenberg , Jone Fine , Arup Roy , Matthew J. McMahon , Mark S. Humayun , James David Welland , Alan M. Horsager , Dao Min Zhou , Amy Hines , Sumit Yadav , Rongqing Dai
IPC分类号： A61N1/372
CPC分类号： A61N1/0543 , A61N1/36046 , A61N1/37247
摘要： The invention is a method of identifying a preferred location for an electrode array to the neural characteristics of an individual subject. The response to electrical neural stimulation varies from subject to subject and array location to array location. Measure of impedance may be used to predict the electrode height from the neural tissue and, thereby, predict the preferred location. Alternatively, electrode height may be measured directly to predict the preferred location.
摘要翻译：本发明是一种将电极阵列的优选位置识别为个体对象的神经特征的方法。对电神经刺激的反应从主体到主体和阵列位置到阵列位置不同。可以使用阻抗测量来预测来自神经组织的电极高度，从而预测优选的位置。或者，可以直接测量电极高度以预测优选位置。

3. 发明申请

US20070072558A1 Digital variable gain mixer 有权
标题翻译：数字可变增益混频器
公开(公告)号：US20070072558A1
公开(公告)日：2007-03-29
申请号：US11394249
申请日：2006-03-30
申请人： Srinath Sridharan , Ahmed Emira , Aria Eshraghi , David Welland
发明人： Srinath Sridharan , Ahmed Emira , Aria Eshraghi , David Welland
IPC分类号： H01Q11/12 , H04B1/04
CPC分类号： H04B1/0475
摘要： A method includes controlling a mixer gain to provide a range of selected power output levels from the mixer using a first control scheme for a low portion of the range and using a second control scheme for a high portion of the range. Using the selected mixer gain, incoming baseband signals may be upconverted in the mixer to a transmission frequency and output from the mixer at the selected power output level.
摘要翻译：一种方法包括：控制混频器增益，以使用第一控制方案从该混频器提供所选择的功率输出电平的范围，并对该范围的高部分使用第二控制方案。使用所选择的混频器增益，输入基带信号可以在混频器中上变频到传输频率，并在所选功率输出电平下从混频器输出。

4. 发明申请

US20060215771A1 Direct digital access arrangement circuitry and method for connecting to phone lines 失效
公开(公告)号：US20060215771A1
公开(公告)日：2006-09-28
申请号：US11398090
申请日：2006-04-05
申请人： Jeffrey Scott , Navdeep Sooch , David Welland
发明人： Jeffrey Scott , Navdeep Sooch , David Welland
IPC分类号： H04L25/00
CPC分类号： H04M1/573 , H04L7/033 , H04L25/0266 , H04L25/06 , H04M1/76 , H04M3/007 , H04M11/06 , H04M19/001 , H04M19/02
摘要： An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.

5. 发明申请

US20080008259A1 Ratiometric clock systems for integrated receivers and associated methods 有权
标题翻译：用于集成接收机和相关方法的比例时钟系统
公开(公告)号：US20080008259A1
公开(公告)日：2008-01-10
申请号：US11900957
申请日：2007-09-14
申请人： G. Tuttle , David Welland , Scott Willingham
发明人： G. Tuttle , David Welland , Scott Willingham
IPC分类号： H04L7/027
CPC分类号： H04B1/30
摘要： A ratiometric clock system for an integrated receiver and associated method are disclosed that provide an advantageous solution for combining digital signal processing (DSP) circuitry on the same integrated circuit as mixer and local oscillator (LO) generation circuitry. The generation circuitry generates an oscillation signal that is passed through a first divider to generate mixing signals for the mixer and that is passed through a second divider to generate a digital clock signal that is utilized by the DSP circuitry. This digital clock signal can be utilized by integrated analog-to-digital conversion circuitry, as well.
摘要翻译：公开了一种用于集成接收机和相关方法的比例时钟系统，其提供用于将数字信号处理（DSP）电路组合在与混频器和本地振荡器（LO）生成电路相同的集成电路上的有利解决方案。产生电路产生振荡信号，该信号通过第一分频器以产生用于混频器的混频信号，并通过第二分频器产生由DSP电路利用的数字时钟信号。该数字时钟信号也可以由集成的模数转换电路使用。

6. 发明申请

US20070071129A1 Edge transceiver architecture and related methods 有权
标题翻译：边缘收发器架构及相关方法
公开(公告)号：US20070071129A1
公开(公告)日：2007-03-29
申请号：US11510339
申请日：2006-08-25
申请人： David Welland
发明人： David Welland
IPC分类号： H04L27/20
CPC分类号： H04L27/0008 , H04B1/04
摘要： In one embodiment, the present invention includes an apparatus having multiple transmission paths, including a first transmission path configured to receive and process baseband data in a first mode of operation to generate a radio frequency (RF) signal for output via a common output path, and a second transmission path configured to receive and process the baseband data in a second mode of operation to generate the RF signal for output via the common output path.
摘要翻译：在一个实施例中，本发明包括具有多个传输路径的设备，包括：第一传输路径，其被配置为在第一操作模式中接收和处理基带数据，以产生用于经由公共输出路径输出的射频（RF）信号; 以及第二传输路径，其被配置为在第二操作模式中接收和处理所述基带数据，以产生所述RF信号以经由所述公共输出路径输出。

7. 发明申请

US20060008075A1 Direct digital access arrangement circuitry and method for connecting DSL circuitry to phone lines 审中-公开
标题翻译：用于将DSL电路连接到电话线的直接数字接入安排电路和方法
公开(公告)号：US20060008075A1
公开(公告)日：2006-01-12
申请号：US10886373
申请日：2004-07-07
申请人： Jeffrey Scott , Navdeep Sooch , David Welland
发明人： Jeffrey Scott , Navdeep Sooch , David Welland
IPC分类号： H04M1/00
CPC分类号： H04M1/738 , H04M11/062
摘要： An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. A bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information. Finally, the isolation system may include a pulse transformer to accommodate ADSL circuitry, whereby power is transmitted through the pulse transformer.
摘要翻译：提供了一种适用于电话，医疗仪器，工业过程控制和其他应用的隔离系统。本发明的优选实施例包括电容隔离屏障，通过数字信号传送数字信号。该系统提供跨越隔离屏障的通信手段，其高度免疫幅度和相位噪声干扰。可以在隔离屏障的一侧采用时钟恢复电路，从跨屏障通信的数字信号提取定时信息，并且滤除在屏障处引入的相位噪声的影响。 Δ-Σ转换器可以设置在隔离屏障的两侧以在模拟和数字域之间转换信号。隔离电源也可以设置在屏障的隔离侧上，由此响应于穿过隔离屏障接收的数字数据产生直流电流。提供了双向隔离系统，由此使用单对隔离电容器实现数字信号的双向通信。在优选实施例中，跨屏障通信的数字数据由与其他数字控制，信令和成帧信息在时间上多路复用的数字delta-sigma数据信号组成。最后，隔离系统可以包括用于容纳ADSL电路的脉冲变压器，由此通过脉冲变压器传输功率。

8. 发明申请

US20060003706A1 Ratiometric transmit path architecture for communication systems 有权
标题翻译：通信系统的比例传输路径架构
公开(公告)号：US20060003706A1
公开(公告)日：2006-01-05
申请号：US11096133
申请日：2005-03-31
申请人： David Welland , Caiyi Wang
发明人： David Welland , Caiyi Wang
IPC分类号： H04B1/40 , H04B1/02 , H01Q11/12 , H04B1/66
CPC分类号： H04B1/403
摘要： A ratiometric transmit path architecture for communication systems and related methods are disclosed. This ratiometric transmit path architecture utilizes a single local oscillator signal and dividers to provide mixing signals for intermediate frequency (IF) mixing circuitry and feedback mixing circuitry, thereby eliminating the need for separate IF and radio frequency (RF) voltage controlled oscillators (VCOs) in prior solutions.
摘要翻译：公开了用于通信系统和相关方法的比例传输路径架构。这种比例传输路径架构利用单个本地振荡器信号和分频器来为中频（IF）混频电路和反馈混频电路提供混频信号，从而消除对单独的IF和射频（RF）压控振荡器（VCO）的需要以前的解决方案。

9. 发明授权

US08193822B2 System and method for determining capacitance value 有权
标题翻译：用于确定电容值的系统和方法
公开(公告)号：US08193822B2
公开(公告)日：2012-06-05
申请号：US12494417
申请日：2009-06-30
申请人： David Welland
发明人： David Welland
IPC分类号： G01R27/26
CPC分类号： G01R27/2605 , H03K17/9622
摘要： A circuit for determining a value of a variable capacitor includes first circuitry for generating a first indication when a variable voltage across the variable capacitor exceeds a threshold voltage. Second circuitry generates a second indication when a reference voltage across a reference capacitor exceeds the threshold voltage. Control logic responsive to the first and second indications generate a control signal indicating whether the first indication or the second indication occurs first. A successive approximation engine generates an N-bit control value responsive to the control signal. A variable current source is responsive to the N-bit control value for generating a variable current to the first circuitry. A reference current source generates a reference current to the second circuitry.
摘要翻译：用于确定可变电容器的值的电路包括当可变电容器两端的可变电压超过阈值电压时产生第一指示的第一电路。当参考电容两端的参考电压超过阈值电压时，第二电路产生第二指示。响应于第一和第二指示的控制逻辑产生指示第一指示或第二指示是否首先出现的控制信号。逐次逼近引擎响应于控制信号产生N位控制值。可变电流源响应于N位控制值以产生到第一电路的可变电流。参考电流源产生到第二电路的参考电流。

10. 发明申请

US20120054379A1 LOW POWER MULTI-TOUCH SCAN CONTROL SYSTEM 审中-公开
标题翻译：低功耗多触控扫描控制系统
公开(公告)号：US20120054379A1
公开(公告)日：2012-03-01
申请号：US12870849
申请日：2010-08-30
申请人： Kafai Leung , Brent Wilson , Yonghong Tao , Shan Wang , Shantonu Bhadury , Suby Pellissery , Raghavendra Pai Kateel , David Welland , David Andreas , Gabriel Vogel
发明人： Kafai Leung , Brent Wilson , Yonghong Tao , Shan Wang , Shantonu Bhadury , Suby Pellissery , Raghavendra Pai Kateel , David Welland , David Andreas , Gabriel Vogel
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F1/3206 , G06F1/3262 , G06F1/3275 , G06F3/0416 , G06F3/044 , G06F2203/04104 , Y02D10/13 , Y02D10/14
摘要： An integrated control circuit is disclosed including a central processing unit operating in a normal full system power mode and in a reduced system low power mode, and a memory. A plurality of peripheral units are provided, at least one of which includes an input/output for interfacing with at least an external system for receiving information therefrom and a process block. The process block processes the received information from the external system and during the processing of the received information, data is stored in the at least one peripheral unit, and data is transferred at least to or at least from the memory. The input/output and process blocks are fully operable in the full system power mode and the reduced system power mode. A direct memory access (DMA) transfers data directly between the at least one peripheral and the memory when such data transfer is required by the peripheral. The DMA operates in a full power DMA mode when data transfer is required and a low power DMA mode when data transfer is not required. The central processing unit is operable, in the normal full system power mode, to interface with the memory and with the at least one peripheral unit to access data stored by the at least one peripheral unit.
摘要翻译：公开了一种集成控制电路，其包括以正常全系统功率模式和降低的系统低功率模式操作的中央处理单元和存储器。提供多个外围单元，其中至少一个包括用于与至少外部系统进行接口以从其接收信息的输入/输出和处理块。处理块处理来自外部系统的接收到的信息，并且在接收到的信息的处理期间，将数据存储在至少一个外围单元中，并且数据至少传送到或至少从存储器传送。输入/输出和过程模块可以在全系统电源模式和降低的系统电源模式下完全工作。直接存储器访问（DMA）在外围设备需要这种数据传输时，直接在至少一个外围设备和存储器之间传输数据。当需要数据传输时，DMA工作在全功率DMA模式，而在不需要数据传输时，DMA工作在低功耗DMA模式。中央处理单元在正常全系统功率模式下可操作地与存储器和至少一个外围单元接口以访问由至少一个外围单元存储的数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式