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1. 发明申请

US20120083913A1 SEMICONDUCTOR LAYER FORMING METHOD AND STRUCTURE 有权
标题翻译：半导体层形成方法和结构
公开(公告)号：US20120083913A1
公开(公告)日：2012-04-05
申请号：US12897021
申请日：2010-10-04
申请人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Nitin Sharma , Tad J. Wilder , Charles B. Winn
发明人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Nitin Sharma , Tad J. Wilder , Charles B. Winn
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/72
摘要： A method of forming and electrical structure. The method includes determining that a first semiconductor device requires an engineering change order (ECO). An additional structure layer required to implement the ECO is determined. A first insertion point location for inserting the additional structure layer within the first semiconductor device is selected. The first insertion point location is associated with a second insertion point location within a design for a second semiconductor device. The second semiconductor device is generated in accordance with the first ECO. The second semiconductor device comprises second structures. The second structures comprise same structures as first structures in the first semiconductor device. The second structures are formed in locations within the second semiconductor device that are associated with locations in the first semiconductor device comprising the first structures. The second semiconductor device comprises the additional structure layer located within the second insertion point location.
摘要翻译：一种形成和电气结构的方法。该方法包括确定第一半导体器件需要工程改变顺序（ECO）。确定实现ECO所需的附加结构层。选择用于将附加结构层插入第一半导体器件内的第一插入点位置。第一插入点位置与用于第二半导体器件的设计内的第二插入点位置相关联。根据第一ECO产生第二半导体器件。第二半导体器件包括第二结构。第二结构包括与第一半导体器件中的第一结构相同的结构。第二结构形成在第二半导体器件内的与包含第一结构的第一半导体器件中的位置相关联的位置。第二半导体器件包括位于第二插入点位置内的附加结构层。

2. 发明授权

US07917348B2 Method of switching external models in an automated system-on-chip integrated circuit design verification system 有权
标题翻译：在自动系统级芯片集成电路设计验证系统中切换外部模型的方法
公开(公告)号：US07917348B2
公开(公告)日：2011-03-29
申请号：US11969991
申请日：2008-01-07
申请人： Robert J. Devins , Robert D. Herzl , David W. Milton
发明人： Robert J. Devins , Robert D. Herzl , David W. Milton
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A system and method for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for selectively connecting one or more of the I/O cores to corresponding I/O driver models; a bus for transferring signals between the I/O controller and the switch; and a test operating system for controlling the switch.
摘要翻译：提供一种用于验证集成电路设计的系统和方法。该系统包括：连接到一个或多个I / O核心的I / O控制器，集成电路设计的I / O核心部分; 具有用于选择性地将一个或多个所述I / O核心连接到相应的I / O驱动器模型的开关的外部存储器映射测试装置; 用于在I / O控制器和开关之间传送信号的总线; 以及用于控制开关的测试操作系统。

3. 发明授权

US07729877B2 Method and system for logic verification using mirror interface 失效
标题翻译：使用镜像接口进行逻辑验证的方法和系统
公开(公告)号：US07729877B2
公开(公告)日：2010-06-01
申请号：US11930820
申请日：2007-10-31
申请人： Robert J. Devins , Paul J. Ferro , Peter D. LaFauci , Kenneth A. Mahler , David W. Milton
发明人： Robert J. Devins , Paul J. Ferro , Peter D. LaFauci , Kenneth A. Mahler , David W. Milton
IPC分类号： G01R31/00 , G01R31/14
CPC分类号： G01R31/318357 , G01R31/319 , G06F17/5022
摘要： Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.
摘要翻译：核心系统芯片（SOC）外部接口的验证经常需要购买昂贵的标准化软件模型来测试外部接口。通常，标准化模型提供比所需更多的功能。可以开发和利用测试模型，而不是标准化模型，但这也会导致成本和延迟。本发明提供了一种有效和经济的替代方案。经过验证的镜像接口或外部接口的副本与标准化控制机制一起使用，以验证外部接口。因为可以利用所有接口I / O连接，因此提供了验证这种接口的成本有效且高可重复使用的方式。

4. 发明申请

US20090267660A1 Circuit and design structure for synchronizing multiple digital signals 失效
标题翻译：用于同步多个数字信号的电路和设计结构
公开(公告)号：US20090267660A1
公开(公告)日：2009-10-29
申请号：US12107847
申请日：2008-04-23
申请人： David W. Milton
发明人： David W. Milton
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , G06F5/06 , H04L7/033
摘要： Disclosed is a circuit configured to synchronize multiple signals received by one clock domain from a different asynchronous clock domain, when simultaneous movement of the signals between the clock domains is intended. In the circuit multiple essentially identical pipelined signal paths receive digital input signals. XOR gates are associated with each of the signal paths. Each XOR gate monitors activity in a given signal path and controls, directly or indirectly (depending upon the embodiment), advancement of signal processing in the other signal path(s) to ensure that, if warranted, output signals at the circuit output nodes are synchronized. In a two-signal path embodiment, advancement of signal processing in one signal path is triggered, whenever transitioning digital signals are detected within the other signal path. In an n-signal path advancement of signal processing is triggered in all signal paths, whenever transitioning digital signals are detected on at least one signal path.
摘要翻译：公开了一种电路，被配置为当希望在时钟域之间同时移动信号时，将来自不同异步时钟域的一个时钟域接收的多个信号同步。在电路中，多个基本相同的流水线信号路径接收数字输入信号。 XOR门与每个信号路径相关联。每个XOR门监视给定信号路径中的活动并且直接或间接地控制（取决于实施例），在另一个信号路径中提高信号处理，以确保如果有必要，在电路输出节点处的输出信号是同步在双信号路径实施例中，每当在另一个信号路径内检测到转换的数字信号时，触发一个信号路径中的信号处理的提前。无论何时在至少一个信号路径上检测到转换数字信号，在所有信号路径中触发信号处理的n信号通路。

5. 发明申请

US20090265677A1 INTEGRATED TEST WAVEFORM GENERATOR (TWG) AND CUSTOMER WAVEFORM GENERATOR (CWG), DESIGN STRUCTURE AND METHOD 有权
标题翻译：集成测试波形发生器（TWG）和客户波形发生器（CWG），设计结构和方法
公开(公告)号：US20090265677A1
公开(公告)日：2009-10-22
申请号：US12104461
申请日：2008-04-17
申请人： Gary D. Grise , Vikram Iyengar , David E. Lackey , David W. Milton
发明人： Gary D. Grise , Vikram Iyengar , David E. Lackey , David W. Milton
IPC分类号： H03K5/156 , G06F1/10 , G06F17/50
CPC分类号： G06F17/505 , G06F1/10 , G06F2217/62 , H03K5/156
摘要： Disclosed are embodiments of a clock generation circuit, a design structure for the circuit and an associated method that provide deskewing functions and that further provide precise timing for both testing and functional operations. Specifically, the embodiments incorporate a deskewer circuit that is capable of receiving waveform signals from both an external waveform generator and an internal waveform generator. The external waveform generator can generate and supply to the deskewer circuit a pair of waveform signals for functional operations. The internal waveform generator can be uniquely configured with control logic and counter logic for generating and supplying a pair of waveform signals to the deskewer circuit for any one of built-in self-test (BIST) operations, macro-test operations, other test operations or functional operations. The deskewer circuit can selectively gate an input clock signal with the waveform signals from either the external or internal waveform generator in order to generate the required output clock signal.
摘要翻译：公开了时钟发生电路的实施例，用于电路的设计结构和相关联的方法，其提供了偏移功能，并进一步为测试和功能操作提供精确的定时。具体地说，这些实施例结合了能够从外部波形发生器和内部波形发生器接收波形信号的偏移电路。外部波形发生器可以生成和提供一个用于功能操作的波形信号。内部波形发生器可以独特地配置控制逻辑和计数器逻辑，用于为内置自检（BIST）操作，宏测试操作，其他测试操作中的任何一个生成和提供一对波形信号到电路板电路或功能操作。该偏移电路可以使用来自外部或内部波形发生器的波形信号选择性地输入输入时钟信号，以便产生所需的输出时钟信号。

6. 发明授权

US07536496B2 Method and apparatus for transmitting data in an integrated circuit 失效
标题翻译：用于在集成电路中传输数据的方法和装置
公开(公告)号：US07536496B2
公开(公告)日：2009-05-19
申请号：US11276449
申请日：2006-02-28
申请人： W. Riyon Harding , David W. Milton , Clarence Rosser Ogilvie , Jason E. Rotella , Paul M. Schanely , Sebastian T. Ventrone
发明人： W. Riyon Harding , David W. Milton , Clarence Rosser Ogilvie , Jason E. Rotella , Paul M. Schanely , Sebastian T. Ventrone
IPC分类号： G06F13/00 , G06F13/42 , G06F13/362 , H04L12/28 , H04L12/56 , H03K17/00
CPC分类号： G06F13/14 , G06F13/362
摘要： A method and apparatus for transmitting data between cores residing in an integrated circuit. Data is transmitted by using hubs located between the cores and an arbiter. The arbiter maintains a table that contains all the valid combinations of routing paths between the cores.
摘要翻译：一种用于在驻留在集成电路中的核之间传送数据的方法和装置。通过使用位于核心和仲裁器之间的集线器来传输数据。仲裁器维护一个表，其中包含核心之间路由路径的所有有效组合。

7. 发明授权

US07515666B2 Method for dynamically changing the frequency of clock signals 失效
标题翻译：动态改变时钟信号频率的方法
公开(公告)号：US07515666B2
公开(公告)日：2009-04-07
申请号：US11161335
申请日：2005-07-29
申请人： David W. Milton , Jason E. Rotella
发明人： David W. Milton , Jason E. Rotella
IPC分类号： H04L7/00
CPC分类号： G06F1/12
摘要： A method and circuit for dynamically changing the frequency of clock signals. The method including: detecting an edge of a first clock signal operating at a first frequency using a second clock signal operating at a second frequency; detecting an edge of the second clock signal using the first clock signal; detecting coincident edges of the first and the second clock signals; and changing the second frequency to a third frequency different from the second frequency upon detection of the coincident edges.
摘要翻译：一种用于动态改变时钟信号频率的方法和电路。该方法包括：使用以第二频率操作的第二时钟信号来检测以第一频率工作的第一时钟信号的边沿; 使用所述第一时钟信号检测所述第二时钟信号的边沿; 检测第一和第二时钟信号的重合边缘; 以及在检测到所述重合边缘时将所述第二频率改变为与所述第二频率不同的第三频率。

8. 发明申请

US20090045839A1 ASIC LOGIC LIBRARY OF FLEXIBLE LOGIC BLOCKS AND METHOD TO ENABLE ENGINEERING CHANGE 审中-公开
标题翻译：柔性逻辑块的ASIC逻辑库和使用工程变更的方法
公开(公告)号：US20090045839A1
公开(公告)日：2009-02-19
申请号：US11876263
申请日：2007-10-22
申请人： Robert D. HERZL , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
发明人： Robert D. HERZL , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
IPC分类号： H03K19/177 , G06F17/50
CPC分类号： G06F17/505
摘要： A chip design methodology and an integrated circuit chip. The methodology includes providing a plurality of logic gates in a net list, wherein each of the logic gates comprises at least one spare input, synthesizing the net list, and connecting the spare inputs for performing an engineering change late in the design process. The invention is also directed to a design structure on which a circuit resides.
摘要翻译：芯片设计方法和集成电路芯片。该方法包括在网络列表中提供多个逻辑门，其中每个逻辑门包括至少一个备用输入，合成网络列表，以及在设计过程的后期连接用于执行工程变更的备用输入。本发明还涉及电路所在的设计结构。

9. 发明授权

US07451070B2 Optimal bus operation performance in a logic simulation environment 有权
标题翻译：逻辑仿真环境中最优总线运算性能
公开(公告)号：US07451070B2
公开(公告)日：2008-11-11
申请号：US10907628
申请日：2005-04-08
申请人： Robert J. Devins , David W. Milton
发明人： Robert J. Devins , David W. Milton
IPC分类号： G06F9/455
CPC分类号： G06F17/5022
摘要： Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable register maintains a count of a number of samples provided the simulator in execution of a transaction on the bus functional model. For each supported bus functional model, a sample count retrieved from the bus functional model and a last sampling value given the hardware assisted simulator is maintained, and a binary convergence algorithm applied to generate sampling values based on the last sampling value given to the hardware assisted simulator and the last actual sampling value used by a given bus functional model for a transaction.
摘要翻译：来自总线功能模型和二进制收敛算法的采样计数反馈是为加速器或硬件辅助模拟器生成最佳采样值。模拟器包括总线功能模型和驱动程序。软件可读寄存器维持在总线功能模型上执行交易的模拟器提供的多个样本的计数。对于每个支持的总线功能模型，维护从总线功能模型检索的样本计数和给定硬件辅助仿真器的最后一个采样值，并应用二进制收敛算法，以根据给予硬件辅助的最后一个采样值来生成采样值模拟器和给定总线功能模型用于交易的最后一个实际采样值。

10. 发明授权

US07353156B2 Method of switching external models in an automated system-on-chip integrated circuit design verification system 有权
标题翻译：在自动系统级芯片集成电路设计验证系统中切换外部模型的方法
公开(公告)号：US07353156B2
公开(公告)日：2008-04-01
申请号：US09683677
申请日：2002-02-01
申请人： Robert J. Devins , Robert D. Herzl , David W. Milton
发明人： Robert J. Devins , Robert D. Herzl , David W. Milton
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A system for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for selectively connecting one or more of the I/O cores to corresponding I/O driver models; a bus for transferring signals between the I/O controller and the switch; and a test operating system for controlling the switch.
摘要翻译：提供一种用于验证集成电路设计的系统。该系统包括：连接到一个或多个I / O核心的I / O控制器，集成电路设计的I / O核心部分; 具有用于选择性地将一个或多个所述I / O核心连接到相应的I / O驱动器模型的开关的外部存储器映射测试装置; 用于在I / O控制器和开关之间传送信号的总线; 以及用于控制开关的测试操作系统。

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