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1. 发明授权

US08189723B2 Method, circuit, and design structure for capturing data across a pseudo-synchronous interface 有权
标题翻译：用于通过伪同步接口捕获数据的方法，电路和设计结构
公开(公告)号：US08189723B2
公开(公告)日：2012-05-29
申请号：US12192571
申请日：2008-08-15
申请人： Malede W. Berhanu , Christopher D. Hanudel , Mark W. Kuemerle , David W. Milton , Clarence R. Ogilvie , Jack R. Smith
发明人： Malede W. Berhanu , Christopher D. Hanudel , Mark W. Kuemerle , David W. Milton , Clarence R. Ogilvie , Jack R. Smith
IPC分类号： H04L7/00
CPC分类号： H03L7/0814 , H04L7/0012 , H04L7/0037
摘要： A method for source synchronous communication. The method includes dynamically adjusting a delay that is applied to a data signal and a remote clock signal until a delayed remote clock signal is synchronized with a local clock signal, and capturing data from a delayed data signal associated with the delay in a local domain.
摘要翻译：一种源同步通信方法。该方法包括动态地调整应用于数据信号和远程时钟信号的延迟，直到延迟的远程时钟信号与本地时钟信号同步，并且从与本地域中的延迟相关联的延迟数据信号中捕获数据。

2. 发明授权

US08181148B2 Method for identifying and implementing flexible logic block logic for easy engineering changes 有权
标题翻译：识别和实现灵活逻辑块逻辑以方便工程变更的方法
公开(公告)号：US08181148B2
公开(公告)日：2012-05-15
申请号：US12014240
申请日：2008-01-15
申请人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
发明人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
IPC分类号： G06F15/04 , G06F17/50
CPC分类号： G06F17/5045
摘要： A chip design methodology. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB).
摘要翻译：芯片设计方法。该方法包括识别工程可变逻辑，并用灵活的逻辑块（FLB）替换所识别的工程可变逻辑。

3. 发明授权

US08141028B2 Structure for identifying and implementing flexible logic block logic for easy engineering changes 有权
标题翻译：用于识别和实现灵活逻辑块逻辑的结构，便于工程变更
公开(公告)号：US08141028B2
公开(公告)日：2012-03-20
申请号：US12054835
申请日：2008-03-25
申请人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
发明人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
IPC分类号： G06F15/04 , G06F17/50
CPC分类号： G06F17/5045
摘要： A design structure for identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit.
摘要翻译：用于识别工程可变逻辑的设计结构，以及用灵活的逻辑块（FLB）替换所识别的工程可变逻辑。该设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。

4. 发明授权

US07768325B2 Circuit and design structure for synchronizing multiple digital signals 失效
标题翻译：用于同步多个数字信号的电路和设计结构
公开(公告)号：US07768325B2
公开(公告)日：2010-08-03
申请号：US12107847
申请日：2008-04-23
申请人： David W. Milton
发明人： David W. Milton
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , G06F5/06 , H04L7/033
摘要： Disclosed is a circuit configured to synchronize multiple signals received by one clock domain from a different asynchronous clock domain, when simultaneous movement of the signals between the clock domains is intended. In the circuit multiple essentially identical pipelined signal paths receive digital input signals. XOR gates are associated with each of the signal paths. Each XOR gate monitors activity in a given signal path and controls, directly or indirectly (depending upon the embodiment), advancement of signal processing in the other signal path(s) to ensure that, if warranted, output signals at the circuit output nodes are synchronized. In a two-signal path embodiment, advancement of signal processing in one signal path is triggered, whenever transitioning digital signals are detected within the other signal path. In an n-signal path advancement of signal processing is triggered in all signal paths, whenever transitioning digital signals are detected on at least one signal path.
摘要翻译：公开了一种电路，被配置为当希望在时钟域之间同时移动信号时，将来自不同异步时钟域的一个时钟域接收的多个信号同步。在电路中，多个基本相同的流水线信号路径接收数字输入信号。 XOR门与每个信号路径相关联。每个XOR门监视给定信号路径中的活动并且直接或间接地控制（取决于实施例），在另一个信号路径中提高信号处理，以确保如果有必要，在电路输出节点处的输出信号是同步在双信号路径实施例中，每当在另一个信号路径内检测到转换的数字信号时，触发一个信号路径中的信号处理的提前。无论何时在至少一个信号路径上检测到转换数字信号，在所有信号路径中触发信号处理的n信号通路。

5. 发明申请

US20080276034A1 Design Structure for Transmitting Data in an Integrated Circuit 审中-公开
标题翻译：集成电路中数据传输的设计结构
公开(公告)号：US20080276034A1
公开(公告)日：2008-11-06
申请号：US12179597
申请日：2008-07-25
申请人： W. Riyon Harding , David W. Milton , Clarence Rosser Ogilvie , Jason E. Rotella , Paul M. Schanely , Sebastian T. Ventrone
发明人： W. Riyon Harding , David W. Milton , Clarence Rosser Ogilvie , Jason E. Rotella , Paul M. Schanely , Sebastian T. Ventrone
IPC分类号： G06F13/00
CPC分类号： G06F17/505
摘要： A design structure, which may be generated by a fabless design company, for transmitting data between cores residing in an integrated circuit. Data is transmitted by using hubs located between the cores and an arbiter. The arbiter maintains a table that contains all the valid combinations of routing paths between the cores.
摘要翻译：可以由无晶圆厂设计公司生成的用于在驻留在集成电路中的核之间传输数据的设计结构。通过使用位于核心和仲裁器之间的集线器来传输数据。仲裁器维护一个表，其中包含核心之间路由路径的所有有效组合。

6. 发明申请

US20080133206A1 METHOD OF SWITCHING EXTERNAL MODELS IN AN AUTOMATED SYSTEM-ON-CHIP INTEGRATED CIRCUIT DESIGN VERIFICATION SYSTEM 有权
标题翻译：在自动系统集成电路设计验证系统中切换外部模型的方法
公开(公告)号：US20080133206A1
公开(公告)日：2008-06-05
申请号：US11969991
申请日：2008-01-07
申请人： Robert J. Devins , Robert D. Herzl , David W. Milton
发明人： Robert J. Devins , Robert D. Herzl , David W. Milton
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A system and method for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for selectively connecting one or more of the I/O cores to corresponding I/O driver models; a bus for transferring signals between the I/O controller and the switch; and a test operating system for controlling the switch.
摘要翻译：提供一种用于验证集成电路设计的系统和方法。该系统包括：连接到一个或多个I / O核心的I / O控制器，集成电路设计的I / O核心部分; 具有用于选择性地将一个或多个所述I / O核心连接到相应的I / O驱动器模型的开关的外部存储器映射测试装置; 用于在I / O控制器和开关之间传送信号的总线; 以及用于控制开关的测试操作系统。

7. 发明申请

US20120083913A1 SEMICONDUCTOR LAYER FORMING METHOD AND STRUCTURE 有权
标题翻译：半导体层形成方法和结构
公开(公告)号：US20120083913A1
公开(公告)日：2012-04-05
申请号：US12897021
申请日：2010-10-04
申请人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Nitin Sharma , Tad J. Wilder , Charles B. Winn
发明人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Nitin Sharma , Tad J. Wilder , Charles B. Winn
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/72
摘要： A method of forming and electrical structure. The method includes determining that a first semiconductor device requires an engineering change order (ECO). An additional structure layer required to implement the ECO is determined. A first insertion point location for inserting the additional structure layer within the first semiconductor device is selected. The first insertion point location is associated with a second insertion point location within a design for a second semiconductor device. The second semiconductor device is generated in accordance with the first ECO. The second semiconductor device comprises second structures. The second structures comprise same structures as first structures in the first semiconductor device. The second structures are formed in locations within the second semiconductor device that are associated with locations in the first semiconductor device comprising the first structures. The second semiconductor device comprises the additional structure layer located within the second insertion point location.
摘要翻译：一种形成和电气结构的方法。该方法包括确定第一半导体器件需要工程改变顺序（ECO）。确定实现ECO所需的附加结构层。选择用于将附加结构层插入第一半导体器件内的第一插入点位置。第一插入点位置与用于第二半导体器件的设计内的第二插入点位置相关联。根据第一ECO产生第二半导体器件。第二半导体器件包括第二结构。第二结构包括与第一半导体器件中的第一结构相同的结构。第二结构形成在第二半导体器件内的与包含第一结构的第一半导体器件中的位置相关联的位置。第二半导体器件包括位于第二插入点位置内的附加结构层。

8. 发明授权

US07917348B2 Method of switching external models in an automated system-on-chip integrated circuit design verification system 有权
标题翻译：在自动系统级芯片集成电路设计验证系统中切换外部模型的方法
公开(公告)号：US07917348B2
公开(公告)日：2011-03-29
申请号：US11969991
申请日：2008-01-07
申请人： Robert J. Devins , Robert D. Herzl , David W. Milton
发明人： Robert J. Devins , Robert D. Herzl , David W. Milton
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A system and method for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for selectively connecting one or more of the I/O cores to corresponding I/O driver models; a bus for transferring signals between the I/O controller and the switch; and a test operating system for controlling the switch.
摘要翻译：提供一种用于验证集成电路设计的系统和方法。该系统包括：连接到一个或多个I / O核心的I / O控制器，集成电路设计的I / O核心部分; 具有用于选择性地将一个或多个所述I / O核心连接到相应的I / O驱动器模型的开关的外部存储器映射测试装置; 用于在I / O控制器和开关之间传送信号的总线; 以及用于控制开关的测试操作系统。

9. 发明授权

US07729877B2 Method and system for logic verification using mirror interface 失效
标题翻译：使用镜像接口进行逻辑验证的方法和系统
公开(公告)号：US07729877B2
公开(公告)日：2010-06-01
申请号：US11930820
申请日：2007-10-31
申请人： Robert J. Devins , Paul J. Ferro , Peter D. LaFauci , Kenneth A. Mahler , David W. Milton
发明人： Robert J. Devins , Paul J. Ferro , Peter D. LaFauci , Kenneth A. Mahler , David W. Milton
IPC分类号： G01R31/00 , G01R31/14
CPC分类号： G01R31/318357 , G01R31/319 , G06F17/5022
摘要： Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.
摘要翻译：核心系统芯片（SOC）外部接口的验证经常需要购买昂贵的标准化软件模型来测试外部接口。通常，标准化模型提供比所需更多的功能。可以开发和利用测试模型，而不是标准化模型，但这也会导致成本和延迟。本发明提供了一种有效和经济的替代方案。经过验证的镜像接口或外部接口的副本与标准化控制机制一起使用，以验证外部接口。因为可以利用所有接口I / O连接，因此提供了验证这种接口的成本有效且高可重复使用的方式。

10. 发明申请

US20090267660A1 Circuit and design structure for synchronizing multiple digital signals 失效
标题翻译：用于同步多个数字信号的电路和设计结构
公开(公告)号：US20090267660A1
公开(公告)日：2009-10-29
申请号：US12107847
申请日：2008-04-23
申请人： David W. Milton
发明人： David W. Milton
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , G06F5/06 , H04L7/033
摘要： Disclosed is a circuit configured to synchronize multiple signals received by one clock domain from a different asynchronous clock domain, when simultaneous movement of the signals between the clock domains is intended. In the circuit multiple essentially identical pipelined signal paths receive digital input signals. XOR gates are associated with each of the signal paths. Each XOR gate monitors activity in a given signal path and controls, directly or indirectly (depending upon the embodiment), advancement of signal processing in the other signal path(s) to ensure that, if warranted, output signals at the circuit output nodes are synchronized. In a two-signal path embodiment, advancement of signal processing in one signal path is triggered, whenever transitioning digital signals are detected within the other signal path. In an n-signal path advancement of signal processing is triggered in all signal paths, whenever transitioning digital signals are detected on at least one signal path.
摘要翻译：公开了一种电路，被配置为当希望在时钟域之间同时移动信号时，将来自不同异步时钟域的一个时钟域接收的多个信号同步。在电路中，多个基本相同的流水线信号路径接收数字输入信号。 XOR门与每个信号路径相关联。每个XOR门监视给定信号路径中的活动并且直接或间接地控制（取决于实施例），在另一个信号路径中提高信号处理，以确保如果有必要，在电路输出节点处的输出信号是同步在双信号路径实施例中，每当在另一个信号路径内检测到转换的数字信号时，触发一个信号路径中的信号处理的提前。无论何时在至少一个信号路径上检测到转换数字信号，在所有信号路径中触发信号处理的n信号通路。

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