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1. 发明申请

US20080133206A1 METHOD OF SWITCHING EXTERNAL MODELS IN AN AUTOMATED SYSTEM-ON-CHIP INTEGRATED CIRCUIT DESIGN VERIFICATION SYSTEM 有权
标题翻译：在自动系统集成电路设计验证系统中切换外部模型的方法
公开(公告)号：US20080133206A1
公开(公告)日：2008-06-05
申请号：US11969991
申请日：2008-01-07
申请人： Robert J. Devins , Robert D. Herzl , David W. Milton
发明人： Robert J. Devins , Robert D. Herzl , David W. Milton
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A system and method for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for selectively connecting one or more of the I/O cores to corresponding I/O driver models; a bus for transferring signals between the I/O controller and the switch; and a test operating system for controlling the switch.
摘要翻译：提供一种用于验证集成电路设计的系统和方法。该系统包括：连接到一个或多个I / O核心的I / O控制器，集成电路设计的I / O核心部分; 具有用于选择性地将一个或多个所述I / O核心连接到相应的I / O驱动器模型的开关的外部存储器映射测试装置; 用于在I / O控制器和开关之间传送信号的总线; 以及用于控制开关的测试操作系统。

2. 发明授权

US06865502B2 Method and system for logic verification using mirror interface 失效
公开(公告)号：US06865502B2
公开(公告)日：2005-03-08
申请号：US09826035
申请日：2001-04-04
申请人： Robert J. Devins , Paul J. Ferro , Peter D. LaFauci , Kenneth A. Mahler , David W. Milton
发明人： Robert J. Devins , Paul J. Ferro , Peter D. LaFauci , Kenneth A. Mahler , David W. Milton
IPC分类号： G01R31/319 , G01R31/14 , G06F19/00
CPC分类号： G01R31/318357 , G01R31/319 , G06F17/5022
摘要： Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.

3. 发明授权

US06539522B1 Method of developing re-usable software for efficient verification of system-on-chip integrated circuit designs 失效
标题翻译：开发可重用软件的方法，用于片上系统集成电路设计的有效验证
公开(公告)号：US06539522B1
公开(公告)日：2003-03-25
申请号：US09494907
申请日：2000-01-31
申请人： Robert J. Devins , Paul G. Ferro , Robert D. Herzl , Mark E. Kautzman , Kenneth A. Mahler , David W. Milton
发明人： Robert J. Devins , Paul G. Ferro , Robert D. Herzl , Mark E. Kautzman , Kenneth A. Mahler , David W. Milton
IPC分类号： G06F1750
CPC分类号： G01R31/318357 , G06F17/5022
摘要： A method for developing re-usable software for the efficient verification of system-on-chip (SOC) integrated circuit designs. The verification software is used to generate and apply test cases to stimulate components of a SOC design (“cores”) in simulation; the results are observed and used to de-bug the design. The software is hierarchical, implementing a partition between upper-level test application code which generates test cases and verifies results, and low-level device driver code which interfaces with a core being simulated, to apply the test case generated by the upper-level code on a hardware level of operations. Test application and supporting low-level device driver pairs are used and re-used to test their corresponding component cores throughout the SOC development process, by creating higher-level test control programs which control selected combinations of the already-developed test application and device driver programs to test combinations of SOC components. The method provides for the efficient verification of SOC designs and, consequently, a reduced time-to-market for SOC products, because as the verification software is developed and stored, it becomes possible to test increasingly complex core combinations by creating relatively few high-level test programs which re-use already-existing lower-level software. Ultimately, the task of verifying a complex SOC design may be simplified to developing a single chip-specific test program which selects from already-existing test application, device driver and test control programs to perform a realistic test of a chip-specific combination of cores.
摘要翻译：一种用于开发用于片上系统（SOC）集成电路设计的有效验证的可重用软件的方法。验证软件用于生成和应用测试用例，以刺激模拟中SOC设计（“核心”）的组件; 观察结果并用于对设计进行设计。该软件是分级的，实现生成测试用例的上级测试应用程序代码和验证结果之间的分区，以及与正在模拟的内核接口的低级设备驱动程序代码，以应用由上级代码生成的测试用例在硬件层面的操作。测试应用程序和支持低级设备驱动程序对被使用并重新用于在SOC开发过程中测试其相应的组件核心，通过创建更高级别的测试控制程序来控制已经开发的测试应用程序和设备驱动程序的选定组合测试SOC组件组合的程序。该方法提供SOC设计的有效验证，从而缩短了SOC产品的上市时间，因为随着验证软件的开发和存储，可以通过创建相对较少的高可用性测试来测试日益复杂的核心组合，重新使用已经存在的低级软件的级别测试程序。最终，可以简化验证复杂SOC设计的任务，以开发单个芯片特定的测试程序，该测试程序从已经存在的测试应用程序，设备驱动程序和测试控制程序中进行选择，以执行芯片特定的内核组合的现实测试。

4. 发明授权

US09367493B2 Method and system of communicating between peer processors in SoC environment 有权
标题翻译：在SoC环境中对等处理器之间进行通信的方法和系统
公开(公告)号：US09367493B2
公开(公告)日：2016-06-14
申请号：US11275091
申请日：2005-12-09
申请人： Robert J. Devins , David W. Milton , Pascal A. Nsame
发明人： Robert J. Devins , David W. Milton , Pascal A. Nsame
IPC分类号： G06F15/173 , G06F13/24 , G06F15/17
CPC分类号： G06F13/24 , G06F15/17
摘要： A method and system comprises transferring data from a first processor to at least one pulse generator directly connected to an interrupt control of at least a second processor. The transferring of the data bypasses memory. The method further includes reading the transferred data directly from the at least one pulse generator by the at least a second processor.
摘要翻译：一种方法和系统包括将数据从第一处理器传送到直接连接到至少第二处理器的中断控制的至少一个脉冲发生器。数据传输绕过内存。该方法还包括由至少第二处理器直接从至少一个脉冲发生器读取传送的数据。

5. 发明授权

US07711534B2 Method and system of design verification 失效
标题翻译：设计验证方法和系统
公开(公告)号：US07711534B2
公开(公告)日：2010-05-04
申请号：US11275093
申请日：2005-12-09
申请人： Robert J. Devins , David W. Milton , Pascal A. Nsame
发明人： Robert J. Devins , David W. Milton , Pascal A. Nsame
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F11/3688
摘要： A method and system comprises extracting resources required to run a discrete test case or set of associated test cases on a design. The method and system further includes building a simulation model based on the extracted resources and executing the simulation model using only the extracted resources, exclusive of an entire design, to test a specific function or group of interrelated functions represented by the discrete test case or set of associated test cases for design verification, and correlating the simulation results with the test plan.
摘要翻译：一种方法和系统包括提取在设计上运行离散测试用例或相关测试用例的集合所需的资源。该方法和系统还包括基于所提取的资源构建仿真模型，并且仅使用所提取的资源（不包括整个设计）来执行仿真模型，以测试由离散测试用例或集合表示的特定功能或相关联的功能组的相关测试用例进行设计验证，并将仿真结果与测试计划相关联。

6. 发明授权

US06487699B1 Method of controlling external models in system-on-chip verification 失效
标题翻译：在片上系统验证中控制外部模型的方法
公开(公告)号：US06487699B1
公开(公告)日：2002-11-26
申请号：US09494230
申请日：2000-01-31
申请人： Robert J. Devins , Robert D. Herzl , David W. Milton , Clarence R. Ogilvie
发明人： Robert J. Devins , Robert D. Herzl , David W. Milton , Clarence R. Ogilvie
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method, system and media for communicating with and controlling design logic modules (“cores”) which are external to a system-on-chip (“SOC”) design during verification of the design. An external memory-mapped test device (“EMMTD”) is coupled between a SOC design being tested in simulation, and cores external to the SOC design. Internal logic in the EMMTD provides for control and status monitoring of an external core coupled to an EMMTD bi-directional bus by enabling functions including driving data on the bus, reading the current state of data on the bus, and capturing positive and negative edge transitions on the bus.
摘要翻译：一种用于在验证设计期间与在片上系统（“SOC”）设计外部通信并控制设计逻辑模块（“核心”）的方法，系统和介质。外部存储器映射测试设备（“EMMTD”）耦合在仿真中被测试的SOC设计和SOC设计之外的核心。 EMMTD中的内部逻辑通过启用功能，包括总线上的驱动数据，读取总线上的数据的当前状态以及捕获正和负边沿转换，提供耦合到EMMTD双向总线的外部核心的控制和状态监视在公交车上。

7. 发明授权

US06427224B1 Method for efficient verification of system-on-chip integrated circuit designs including an embedded processor 失效
标题翻译：有效验证包括嵌入式处理器在内的片上系统集成电路设计的方法
公开(公告)号：US06427224B1
公开(公告)日：2002-07-30
申请号：US09494564
申请日：2000-01-31
申请人： Robert J. Devins , Mark E. Kautzman , Kenneth A. Mahler , David W. Milton
发明人： Robert J. Devins , Mark E. Kautzman , Kenneth A. Mahler , David W. Milton
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method for using verification software for testing a system-on-chip (SOC) design including an embedded processor. The verification software is used to generate and apply test cases to stimulate the SOC design in simulation; the results are observed and used to de-bug the design. Verification of a SOC design which includes an embedded processor is typically very slow. To provide for a speed-up mode of verification in such a case, in the method of the present invention, verification software is partitioned into higher-level control code and lower-level device driver code. The higher-level code performs such functions as decision-making, test initialization, test randomization, multi-tasking, and comparison of test results with expected results. The low-level code interfaces with a core being simulated, to apply the test case generated by the upper-level code on a hardware level of operations. The partitioning of the verification software as described above allows for a “split-domain” mode of verification in which only the low-level code is executed by a simulated processor model, while the rest of the code executes externally to the simulator. Because most of the verification software executes externally to the simulator while only the low-level code executes on the simulated processor, the overhead of performing the high-level functions is removed from the simulator. As a result, faster verification is enabled.
摘要翻译：一种使用验证软件来测试包括嵌入式处理器在内的片上系统（SOC）设计的方法。验证软件用于生成和应用测试用例，以刺激模拟中的SOC设计; 观察结果并用于对设计进行设计。包括嵌入式处理器的SOC设计的验证通常非常慢。为了在这种情况下提供加速验证模式，在本发明的方法中，验证软件被分为更高级别的控制代码和较低级别的设备驱动程序代码。上级代码执行决策，测试初始化，测试随机化，多任务处理以及测试结果与预期结果的比较等功能。低级代码接口与核心正在被模拟，以便在硬件级别的操作上应用上层代码生成的测试用例。如上所述的验证软件的划分允许“分割域”验证模式，其中只有低级代码由模拟处理器模型执行，而其余代码在模拟器外部执行。因为大多数验证软件在模拟器外部执行，而仅在模拟处理器上执行低级代码，所以执行高级功能的开销从模拟器中移除。因此，启用更快的验证。

8. 发明授权

US08140314B2 Optimal bus operation performance in a logic simulation environment 有权
标题翻译：逻辑仿真环境中最优总线运算性能
公开(公告)号：US08140314B2
公开(公告)日：2012-03-20
申请号：US12228587
申请日：2008-08-14
申请人： Robert J. Devins , David W. Milton
发明人： Robert J. Devins , David W. Milton
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable register maintains a count of a number of samples provided the simulator in execution of a transaction on the bus functional model. For each supported bus functional model, a sample count retrieved from the bus functional model and a last sampling value given the hardware assisted simulator is maintained, and a binary convergence algorithm applied to generate sampling values based on the last sampling value given to the hardware assisted simulator and the last actual sampling value used by a given bus functional model for a transaction.
摘要翻译：来自总线功能模型和二进制收敛算法的采样计数反馈是为加速器或硬件辅助模拟器生成最佳采样值。模拟器包括总线功能模型和驱动程序。软件可读寄存器维持在总线功能模型上执行交易的模拟器提供的多个样本的计数。对于每个支持的总线功能模型，维护从总线功能模型检索的样本计数和给定硬件辅助仿真器的最后一个采样值，并应用二进制收敛算法，以根据给予硬件辅助的最后一个采样值来生成采样值模拟器和给定总线功能模型用于交易的最后一个实际采样值。

9. 发明授权

US07849362B2 Method and system of coherent design verification of inter-cluster interactions 有权
标题翻译：集群间相互作用的连贯设计验证方法和系统
公开(公告)号：US07849362B2
公开(公告)日：2010-12-07
申请号：US11275092
申请日：2005-12-09
申请人： Robert J. Devins , David W. Milton , Pascal A. Nsame
发明人： Robert J. Devins , David W. Milton , Pascal A. Nsame
IPC分类号： G06F11/00
CPC分类号： G06F11/263 , G06F11/261
摘要： A method and system comprises creating a test case that is dependent upon known sequences and executing the test case on an originating processor until it reaches a known point. The method further includes executing the test case on a different processor to perform an action and informing the originating processor that the action was taken. The action is verified as being occurred with the originating processor.
摘要翻译：一种方法和系统包括创建依赖于已知序列的测试用例，并且在始发处理器上执行测试用例，直到到达已知点。该方法还包括在不同的处理器上执行测试用例以执行动作，并通知始发处理器已采取动作。该动作被验证为与始发处理器一起发生。

10. 发明申请

US20080312896A1 Optimal bus operation performance in a logic simulation environment 有权
公开(公告)号：US20080312896A1
公开(公告)日：2008-12-18
申请号：US12228587
申请日：2008-08-14
申请人： Robert J. Devins , David W. Milton
发明人： Robert J. Devins , David W. Milton
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable register maintains a count of a number of samples provided the simulator in execution of a transaction on the bus functional model. For each supported bus functional model, a sample count retrieved from the bus functional model and a last sampling value given the hardware assisted simulator is maintained, and a binary convergence algorithm applied to generate sampling values based on the last sampling value given to the hardware assisted simulator and the last actual sampling value used by a given bus functional model for a transaction.

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