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1. 发明授权

US06426658B1 Buffers with reduced voltage input/output signals 有权
标题翻译：具有降低电压输入/输出信号的缓冲器
公开(公告)号：US06426658B1
公开(公告)日：2002-07-30
申请号：US09676864
申请日：2000-09-29
申请人： Gerhard Mueller , David Russell Hanson
发明人： Gerhard Mueller , David Russell Hanson
IPC分类号： H03K190185
CPC分类号： H03K19/018521
摘要： A buffer circuit that operates with reduced voltage input and output signals receives an input signal having reduced voltage range and generates an output signal with the reduced voltage range. The reduced voltage range is from 0 volts to VRED, where VRED is less than VCC, the voltage used to operate most of the logic in the integrated circuit. The use of a buffer circuit that receives and generates signals with a reduced voltage range advantageously reduces power consumption.
摘要翻译：以降低的电压输入和输出信号工作的缓冲电路接收具有降低的电压范围的输入信号并产生具有降低的电压范围的输出信号。降低的电压范围是从0伏到VRED，其中VRED小于VCC，用于操作集成电路中大部分逻辑的电压。使用接收和产生具有降低的电压范围的信号的缓冲电路有利地降低功耗。

2. 发明授权

US06529054B1 Prefetch architectures for data and time signals in an integrated circuit and methods therefor 有权
标题翻译：在集成电路中预取数据和时间信号的架构及其方法
公开(公告)号：US06529054B1
公开(公告)日：2003-03-04
申请号：US09425329
申请日：1999-10-22
申请人： David Russell Hanson , Gerhard Mueller
发明人： David Russell Hanson , Gerhard Mueller
IPC分类号： H03L716
CPC分类号： G11C7/1066 , G11C7/1006 , G11C7/1039 , G11C7/1051 , G11C7/1078 , G11C7/22 , G11C11/4096 , G11C2207/107 , H04J3/0685 , H04L7/0008
摘要： A synchronized data capture circuit configured to synchronize capturing of data in a first plurality of data signals with a first plurality of timing signals to output a synchronized data capture signal. The synchronized data capture circuit includes a timer generator having a first timer generator output. The timer generator is coupled to receive the first plurality of timing signals and to serially output on the first timer generator output, as a first high frequency timing pulse stream, first timing pulses responsive to timing pulses of the plurality of timing signals. The first high frequency timing pulse stream has a timing pulse stream frequency that is higher than a timing input frequency associated with one of the first plurality of timing signals. The synchronized data capture circuit also includes first plurality of data driver circuits coupled to receive the first plurality of data signals and the plurality of timing signals. The first plurality of data driver circuits are configured to serially output, as a first high frequency data stream, first data pulses responsive to the timing pulses of the plurality of timing signals and data pulses of the first plurality of data signal. The first high frequency data stream has a data stream frequency that is higher than a data input frequency associated with one of the first plurality of data signals. The synchronized data capture circuit further includes a first data clocking circuit coupled to receive the first high frequency data stream and the first high frequency timing pulse stream to synchronize capture of data in the first high frequency data stream using the first high frequency timing pulse stream to output the synchronized data capture signal, wherein the synchronized data capture signal has a data output frequency that is higher than the timing input frequency and the data input frequency.
摘要翻译：一种同步数据捕获电路，被配置为将第一多个数据信号中的数据的采集与第一多个定时信号同步，以输出同步的数据捕获信号。同步数据捕获电路包括具有第一定时发生器输出的定时发生器。定时器发生器被耦合以接收第一多个定时信号，并且在第一定时器发生器输出上串行地输出作为第一高频定时脉冲流的响应于多个定时信号的定时脉冲的第一定时脉冲。第一高频定时脉冲流具有比与第一多个定时信号之一相关联的定时输入频率高的定时脉冲流频率。同步数据捕获电路还包括耦合以接收第一多个数据信号和多个定时信号的第一多个数据驱动器电路。第一多个数据驱动器电路被配置为响应于多个定时信号的定时脉冲和第一多个数据信号的数据脉冲串行地输出第一数据脉冲作为第一高频数据流。第一高频数据流具有比与第一多个数据信号之一相关联的数据输入频率高的数据流频率。同步数据捕获电路还包括第一数据时钟电路，其耦合以接收第一高频数据流和第一高频定时脉冲流，以使用第一高频定时脉冲流将第一高频数据流中的数据捕获同步到输出同步数据捕获信号，其中同步数据捕获信号具有高于定时输入频率和数据输入频率的数据输出频率。

3. 发明授权

US06799290B1 Data path calibration and testing mode using a data bus for semiconductor memories 失效
标题翻译：使用半导体存储器的数据总线的数据路径校准和测试模式
公开(公告)号：US06799290B1
公开(公告)日：2004-09-28
申请号：US09512756
申请日：2000-02-25
申请人： Toshiaki Kirihata , Gerhard Mueller , David Russell Hanson
发明人： Toshiaki Kirihata , Gerhard Mueller , David Russell Hanson
IPC分类号： G11C2900
CPC分类号： G11C29/02
摘要： A method for testing a data path for a semiconductor memory device, in accordance with the present invention, includes providing a semiconductor memory device including a plurality of stages in a data path, and transferring data into the data path. Components are disabled to isolate at least one stage of the plurality of stages such that data written to or read from the at least one stage is available at an output. The data at the output is preferably compared to expected data. Alternately, system level calibration between devices may be performed to ensure proper communication between devices without destroying data in a memory array and making a dynamic data skew calibration possibly while running an application.
摘要翻译：根据本发明的用于测试半导体存储器件的数据路径的方法包括提供包括数据路径中的多个级并将数据传送到数据路径的半导体存储器件。组件被禁用以隔离多个级中的至少一个级，使得写入或从至少一个级读取的数据在输出端可用。优选地将输出端的数据与预期数据进行比较。或者，可以执行设备之间的系统级校准，以确保设备之间的正确通信，而不会破坏存储器阵列中的数据并且在运行应用时可能进行动态数据偏移校准。

4. 发明授权

US06668031B1 Synchronized data capturing circuits using reduced voltage levels and methods therefor 有权
标题翻译：使用降低电压电平的同步数据采集电路及其方法
公开(公告)号：US06668031B1
公开(公告)日：2003-12-23
申请号：US09377588
申请日：1999-08-19
申请人： David Russell Hanson , Gerhard Mueller
发明人： David Russell Hanson , Gerhard Mueller
IPC分类号： H04L700
CPC分类号： G11C7/1078 , H04L7/0008
摘要： A synchronized data capture circuit configured to synchronize capturing of data in a data signal with a timing signal in an integrated circuit. The synchronized data circuit employs voltage signals having a reduced voltage level, the data signal and the timing signal having a first voltage level higher than the reduced voltage level. The synchronized data capture circuit includes a timing driver circuit arranged to receive the timing signal. The timing driver circuit outputs a reduced voltage timing signal having the reduced voltage level. There is included a data driver circuit arranged to receive the data signal and the timing signal, the data driver outputting a reduced voltage clocked data signal having the reduced voltage level. There is further included a data clocking circuit coupled to the timing driver circuit and the data driver circuit. The data clocking circuit is arranged to receive the reduced voltage timing signal and the reduced voltage clocked data signal. The data clocking circuit outputs a synchronized capture data signal having the first voltage level higher than the reduced voltage level.
摘要翻译：一种同步数据捕获电路，被配置为将数据信号中的数据的捕获与集成电路中的定时信号同步。同步数据电路采用具有降低的电压电平的电压信号，数据信号和定时信号具有高于降低的电压电平的第一电压电平。同步数据捕获电路包括布置成接收定时信号的定时驱动器电路。定时驱动器电路输出具有降低的电压电平的降低电压定时信号。包括数据驱动器电路，其布置成接收数据信号和定时信号，数据驱动器输出具有降低的电压电平的降低电压的时钟数据信号。还包括耦合到定时驱动器电路和数据驱动器电路的数据时钟电路。数据时钟电路被布置为接收降低的电压定时信号和降低的电压时钟数据信号。数据时钟电路输出具有高于降低的电压电平的第一电压电平的同步捕获数据信号。

5. 发明授权

US06215349B1 Capacitive coupled driver circuit 有权
标题翻译：电容耦合驱动电路
公开(公告)号：US06215349B1
公开(公告)日：2001-04-10
申请号：US09265253
申请日：1999-03-09
申请人： David Russell Hanson , Gerhard Mueller
发明人： David Russell Hanson , Gerhard Mueller
IPC分类号： H03K1716
CPC分类号： G11C7/1069 , G11C7/1012 , G11C7/1048 , G11C7/1051 , G11C11/4096 , H03K19/01707 , H03K19/01728
摘要： A high performance driver circuit is described. The driver produces increased current flow at its output to decrease charging time. Increased current flow is achieved by providing an overdrive circuit that provides a voltage offset to increase the magnitude of the overdrive voltage.
摘要翻译：描述高性能驱动电路。驱动器在其输出端产生增加的电流，以减少充电时间。通过提供提供电压偏移以增加过载驱动电压的幅度的过驱动电路来实现增加的电流。

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